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ST7FLITE25F2M6 Datasheet(PDF) 88 Page - STMicroelectronics |
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ST7FLITE25F2M6 Datasheet(HTML) 88 Page - STMicroelectronics |
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88 / 166 page ![]() On-chip peripherals ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 88/166 Doc ID 8349 Rev 5 11.3.5 Interrupts Note: The TBxF and ICF interrupt events are connected to separate interrupt vectors (see Interrupts chapter). They generate an interrupt if the enable bit is set in the LTCSR1 or LTCSR2 register and the interrupt mask in the CC register is reset (RIM instruction). 11.3.6 Register description Lite timer control/status register 2 (LTCSR2) Read / Write Reset Value: 0000 0000 (00h) ● Bits 7:2 = Reserved, must be kept cleared. ● Bit 1 = TB2IE Timebase 2 Interrupt enable This bit is set and cleared by software. 0: Timebase (TB2) interrupt disabled 1: Timebase (TB2) interrupt enabled ● Bit 0 = TB2F Timebase 2 Interrupt Flag This bit is set by hardware and cleared by software reading the LTCSR register. Writing to this bit has no effect. 0: No Counter 2 overflow 1: A Counter 2 overflow has occurred. Table 38. TBxF and ICF interrupt events Interrupt event Event flag Enable Control bit Exit from WAIT Exit from ACTIVE- HALT Exit from HALT Timebase 1 event TB1F TB1IE Yes Yes No Timebase 2 event TB2F TB2IE Yes No No IC event ICF ICIE Yes No No 7 0 000 00 0 TB2IE TB2F |
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