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L7980ATR Datasheet(PDF) 20 Page - STMicroelectronics |
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L7980ATR Datasheet(HTML) 20 Page - STMicroelectronics |
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20 / 44 page ![]() Application informations L7980 20/44 Doc ID 15181 Rev 4 Equation 16 where: Equation 17 Equation 18 As seen in Chapter 5.3 two different kind of network can compensate the loop. In the two following paragraph the guidelines to select the Type II and Type III compensation network are illustrated. 6.4.1 Type III compensation network The methodology to stabilize the loop consists of placing two zeros to compensate the effect of the LC double pole, so increasing phase margin; then to place one pole in the origin to minimize the dc error on regulated output voltage; finally to place other poles far away the zero dB frequency. If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a frequency higher than the desired bandwidth (that is: 2 π∗ESR∗COUT<1/BW), the type III compensation network is needed. Multi layer ceramic capacitors (MLCC) have very low ESR (<1m Ω), with very high frequency zero, so type III network is adopted to compensate the loop. In Figure 10 the type III compensation network is shown. This network introduces two zeros (fZ1, fZ2) and three poles (fP0, fP1, fP2). They expression are: Equation 19 G LC s () 1 s 2 π f zESR ⋅ -------------------------- + 1 s 2 π Qf ⋅ LC ⋅ ---------------------------- s 2 π f LC ⋅ ------------------- ⎝⎠ ⎛⎞ 2 ++ ------------------------------------------------------------------------- = f LC 1 2 π LC OUT ⋅ 1 ESR R OUT --------------- + ⋅⋅ ------------------------------------------------------------------------ = f zESR 1 2 π ESR C OUT ⋅⋅ -------------------------------------------- = , Q R OUT LC OUT R OUT ESR + () ⋅⋅ ⋅ LC OUT R OUT ESR ⋅⋅ + ------------------------------------------------------------------------------------------ R OUT V OUT I OUT -------------- = , = f Z1 1 2 π C 3 R 1 R 3 + () ⋅⋅ ------------------------------------------------ = f Z2 1 2 π R 4 C 4 ⋅⋅ ------------------------------ = , |
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