ADS5522IPAP datasheet(25/32 Pages) TI

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ADS5522

CLKP

CLKM

0.01 F

SquareWave

orSineW ave

(3VPP)

0.01 F

100

Clock Duty Cycle

− %

SFDR

SNR

IN = 20MHz

0.01 F

ADS5522

CLKM

CLKP

DifferentialSquareWave

orSineWave

(3VPP)

Differential Clock Amplitude

− V

0.5

1.0

1.5

2.0

2.5

3.0

IN = 70MHz

SFDR

SNR

ADS5522

SBAS320C – MAY 2004 – REVISED FEBRUARY 2007

When driven with a single-ended CMOS clock input,

it is best to connect CLKM (pin 11) to ground with a

0.01-

µF capacitor, while CLKP is ac-coupled with a

0.01-

µF capacitor to the clock source, as shown in

Figure 44.

Figure 44. AC-Coupled, Single-Ended Clock Input

The ADS5522 clock input can also be driven

Figure 46. AC Performance vs Clock Duty Cycle

differentially,

reducing

susceptibility

common-mode noise. In this case, it is best to

Bandpass filtering of the source can help produce a

connect both clock inputs to the differential input

50% duty cycle clock and reduce the effect of jitter.

clock signal with 0.01-

µF capacitors, as shown in

When using a sinusoidal clock, the clock jitter further

Figure 45.

improves as the amplitude is increased. In that

sense, using a differential clock allows for the use of

larger amplitudes without exceeding the supply rails

and absolute maximum ratings of the ADC clock

input. Figure 47 shows the performance variation of

the device versus input clock amplitude. For detailed

clocking

schemes

based

transformer

PECL-level clocks, see the ADS5522EVM User's

Guide (SLWU010), available for download from

www.ti.com.

Figure 45. AC-Coupled, Differential Clock Input

For

high

input

frequency

sampling,

recommended to use a clock source with low jitter.

Additionally, the internal ADC core uses both edges

of the clock for the conversion process. This means

that, ideally, a 50% duty cycle should be provided.

Figure 46 shows the performance variation of the

ADC versus clock duty cycle.

Figure 47. AC Performance vs Clock Amplitude

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