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ADC0811 Datasheet(PDF) 7 Page - National Semiconductor (TI) |
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ADC0811 Datasheet(HTML) 7 Page - National Semiconductor (TI) |
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7 / 14 page  Timing Diagrams (Continued) CS High During Conversion TLH5587 – 4 CS Low During Conversion TLH5587 – 5 Note DO and DI lines share the 8-bit IO shift register(see Functional Block Diagram) Since the MUX address bits are shifted in on SCLK rising edges while SCLK falling edges shift out conversion data on DO the eighth falling edge of SCLK will shift out the MSB MUX address bit (A7) on DO Thus if addressing channels CH8–CH10 a high DO will occur momentarily (one w2 clock period) until the 8-bit IO shift register is cleared by the internal EOC signal Channel Addressing Table TABLE I ADC 0811 Channel Addressing MUX ADDRESS ANALOG CHANNEL A7 A6 A5 A4 A3 A2 A1 A0 SELECTED 0 0 0 0 XXXX CH0 0 0 0 1 XXXX CH1 0 0 1 0 XXXX CH2 0 0 1 1 XXXX CH3 0 1 0 0 XXXX CH4 0 1 0 1 XXXX CH5 0 1 1 0 XXXX CH6 0 1 1 1 XXXX CH7 1 0 0 0 XXXX CH8 1 0 0 1 XXXX CH9 1 0 1 0 XXXX CH10 1 0 1 1 XXXX VTEST 1 1 XXXXXX LOGIC TEST MODE Analog channel inputs CH0 thru CH3 are logic outputs 7 |
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