ADC10321 datasheet(7/26 Pages) TI1

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ADC10321

www.ti.com

SNAS028F – JUNE 2000 – REVISED MAY 2013

DC AND LOGIC ELECTRICAL CHARACTERISTICS

The following specifications apply for VA = +5.0VDC, VD = +5.0VDC, VD I/O = 5.0VDC, VREF+ = +3.5VDC, VREF− = +1.5VDC, CL =

20 pF, fCLK = 20MHz, RS = 25Ω. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C

(1)

Symbol

Parameter

Conditions

Typical(2)

Limits(3)

Units

CLK, OE, PD, Digital Input Characteristics

VIH

Logical "1" Input Voltage

VD = 5.5V

2.0

V(min)

VIL

Logical "0" Input Voltage

VD = 4.5V

1.0

V(max)

IIH

Logical "1" Input Current

VIH = VD

µA

IIL

Logical "0" Input Current

VIL = DGND

−10

µA

D00 - D13 Digital Output Characteristics

VD I/O = + 4.5V, IOUT = −0.5mA

4.0

V(min)

VOH

Logical "1" Output Voltage

VD I/O = + 2.7V, IOUT = −0.5mA

2.4

V(min)

VD I/O = + 4.5V, IOUT = −1.6mA

0.4

V(max)

VOL

Logical "0" Output Voltage

VD I/O = + 2.7V, IOUT = −1.6mA

0.4

V(max)

VOUT = DGND

−10

µA

IOZ

TRI-STATE Output Current

VOUT = VD

µA

Output Short Circuit Current

VD I/O = 3V

±12

IOS

VD I/O = 5V

±25

Power Supply Characteristics

PD = LOW, Ref not included

14.5

Analog Supply Current

mA(max)

PD = HIGH, Ref not included

0.5

PD = LOW, Ref not included

ID + IDI/O

Digital Supply Current

mA(max)

PD = HIGH, Ref not included

0.2

Power Consumption

110

mW (max)

(1)

The inputs are protected as shown below. Input voltage magnitudes up to 500mV beyond the supply rails will not damage this device.

However, errors in the A/D conversion can occur if the input goes above VA or below AGND by more than 300 mV. See Figure 1,

Figure 2 and Figure 3.

(2)

Typical figures are at TA = TJ = 25°C, and represent most likely parametric norms.

(3)

Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).

AC ELECTRICAL CHARACTERISTICS

The following specifications apply for VA = +5.0VDC, VD I/O = 5.0VDC, VREF+ = +3.5VDC, VREF− = +1.5VDC, fCLK = 20MHz, trc = tfc

= 5ns, RS = 25Ω. CL (data bus loading) = 20 pF, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C

(1)

Units

Symbol

Parameter

Conditions

Typical(2)

Limits(3)

(Limits)

fCLK1

Maximum Clock Frequency

MHz(min)

fCLK2

Minimum Clock Frequency

MHz(max)

tCH

Clock High Time

ns(min

tCL

Clock Low Time

ns(min)

%(min)

Duty Cycle

%(max)

Pipeliine Delay (Latency)

2.0

Clock Cycles

trc, tfc

Clock Input Rise and Fall Time

ns(max)

tr, tf

Output Rise and Fall Times

tOD

Fall of CLK to data valid

ns(max)

tOH

Output Data Hold Time

(1)

The inputs are protected as shown below. Input voltage magnitudes up to 500mV beyond the supply rails will not damage this device.

However, errors in the A/D conversion can occur if the input goes above VA or below AGND by more than 300 mV. See Figure 1,

Figure 2 and Figure 3.

(2)

Typical figures are at TA = TJ = 25°C, and represent most likely parametric norms.

(3)

Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).

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