MSP4428G datasheet(13/85 Pages) MICRONAS

13 / 85 page

PRELIMINARY DATA SHEET

MSP 44x8G

Micronas

2.5.2. Main and Aux Outputs

The Main and Aux output channels are adjustable in

volume. A square wave beeper with adjustable fre-

quency and volume can be added to them.

2.5.3. Quasi-Peak Detector

The Quasi-Peak Readout register can be used to read

out the quasi-peak level of any input source. The fea-

ture is based on following filter time constants:

– attack time: 1.3 ms

– decay time: 37 ms

2.6. SCART Signal Routing

2.6.1. SCART DSP In and SCART Out Select

The SCART DSP Input Select and SCART Output

Select blocks include full matrix switching facilities. To

design a TV set with four pairs of SCART-inputs and

two pairs of SCART-outputs, no external switching

hardware is required. The switches are controlled by

the ACB user register (see page 31).

2.6.2. Stand-by Mode

If the MSP 44x8G is switched off by first pulling

STANDBYQ low and then (after >1

µs delay) switching

off the 5-V, but keeping the 8-V power supply (‘Stand-

by’-mode), the SCART switches maintain their posi-

tion and function. This allows the copying from

selected SCART-inputs to SCART-outputs in the TV

set’s stand-by mode.

In case of power on or starting from stand-by (see

details on the power-up sequence in Fig. 4–20 on

page 56), all internal registers except the ACB register

(page 31) are reset to the default configuration (see

Table 3–5 on page 18). The reset position of the ACB

into the Baseband Processing part (subaddress

12hex). By transmitting the ACB register first, the reset

state can be redefined.

2.7. I2S Bus Interfaces

The MSP 44x8G has two kinds of interfaces: synchro-

nous master/slave input/output interfaces running on

48 kHz and an asynchronous slave interface.

The interfaces accept a variety of formats with different

sample width, bit-orientation, and wordstrobe timing.

All I2S options are set by means of the MODUS or

I2S_CONFIG register.

2.7.1. Synchronous I2S-Interface(s)

The synchronous I2S bus interface consists of the

pins:

– I2S_DA_IN1, I2S_DA_IN2/3 (I2S_DA_IN2 in

PQFP80 package):

I2S serial data input, 16, 18...32 bits per sample.

– I2S_DA_OUT:

I2S serial data output, 16, 18...32 bits per sample.

– I2S_CL:

I2S serial clock.

– I2S_WS:

I2S word strobe signal defines the left and right

sample.

If the MSP 44x8G serves as the master on the I2S

interface, the clock and word strobe lines are driven by

the MSP. In this mode, only 16, 32 bits per sample can

be selected. In slave mode, these lines are input to the

MSP 44x8G and the MSP clock is synchronized to

384 times the I2S_WS rate (48 kHz). NICAM operation

is not possible in slave mode.

An I2S timing diagram is shown in Fig. 4–22 on

page 59.

2.7.2. Asynchronous I2S-Interface

The asynchronous I2S slave interface allows the

reception of digital stereo signals with arbitrary sample

rates from 5 to 50 kHz. The synchronization is per-

formed by means of an adaptive sample rate con-

verter. No oversampling clock is required.

The following pins are used for the asynchronous I2S

bus interface:

– I2S_WS3 (serves only as input)

– I2S_CL3 (serves only as input)

– I2S_DA_IN2/3 (I2S_DA_IN3 in PQFP80 package).

The interface accepts I2S-input streams with MSB first

and with sample widths of 16,18...32 bits. With left/

right alignment and wordstrobe timing polarity, there

are additional parameters available for the adaption to

a variety of formats in the I2S-CONFIG register (see

page 24).

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