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ST92185B Datasheet(PDF) 77 Page - STMicroelectronics |
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ST92185B Datasheet(HTML) 77 Page - STMicroelectronics |
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77 / 178 page  77/178 ST92185B - TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d) 7.1.4 WDT Interrupts The Timer/Watchdog issues an interrupt request at every End of Count, when this feature is ena- bled. A pair of control bits, IA0S (EIVR.1, Interrupt A0 se- lection bit) and TLIS (EIVR.2, Top Level Input Se- lection bit) allow the selection of 2 interrupt sources (Timer/Watchdog End of Count, or External Pin) handled in two different ways, as a Top Level Non Maskable Interrupt (Software Reset), or as a source for channel A0 of the external interrupt logic. A block diagram of the interrupt logic is given in Figure 3. Note: Software traps can be generated by setting the appropriate interrupt pending bit. Table 1 below, shows all the possible configura- tions of interrupt/reset sources which relate to the Timer/Watchdog. A reset caused by the watchdog will set bit 6, WDGRES of R242 - Page 55 (Clock Flag Regis- ter). See section CLOCK CONTROL REGIS- TERS. Figure 46. Interrupt Sources Table 14. Interrupt Configuration Legend: WDG = Watchdog function SW TRAP = Software Trap Note: If IA0S and TLIS = 0 (enabling the Watchdog EOC as interrupt source for both Top Level and INTA0 interrupts), only the INTA0 interrupt is taken into account. TIMER WATCHDOG RESET WDGEN (WCR.6) INTA0 REQUEST IA0S (EIVR.1) MUX 0 1 INT0 MUX 0 1 TOP LEVEL INTERRUPT REQUEST VA00293 TLIS (EIVR.2) NMI Control Bits Enabled Sources Operating Mode WDGEN IA0S TLIS Reset INTA0 Top Level 0 0 0 0 0 0 1 1 0 1 0 1 WDG/Ext Reset WDG/Ext Reset WDG/Ext Reset WDG/Ext Reset SW TRAP SW TRAP Ext Pin Ext Pin SW TRAP Ext Pin SW TRAP Ext Pin Watchdog Watchdog Watchdog Watchdog 1 1 1 1 0 0 1 1 0 1 0 1 Ext Reset Ext Reset Ext Reset Ext Reset Timer Timer Ext Pin Ext Pin Timer Ext Pin Timer Ext Pin Timer Timer Timer Timer |
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