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EM357-RTR Datasheet(PDF) 146 Page - Silicon Laboratories |
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EM357-RTR Datasheet(HTML) 146 Page - Silicon Laboratories |
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146 / 241 page  Rev 1.3 146 TIM_URS [2] RW Update Request Source. 0: When enabled, update interrupt requests are sent as soon as registers are updated (counter overflow/underflow, setting the TIM_UG bit, or update generation through the slave mode controller). 1: When enabled, update interrupt requests are sent only when the counter reaches over- flow or underflow. TIM_UDIS [1] RW Update Disable. 0: A UEV is generated as soon as a counter overflow occurs, a software update is gener- ated, or a hardware reset is generated by the slave mode controller. Shadow registers are then loaded with their buffer register values. 1: A UEV is not generated and shadow registers keep their value (TIMx_ARR, TIMx- _PSC, TIMx_CCRy). The counter and the prescaler are reinitialized if the TIM_UG bit is set or if a hardware reset is received from the slave mode controller. TIM_CEN [0] RW Counter Enable. 0: Counter disabled. 1: Counter enabled. Note: External clock, gated mode and encoder mode can work only if the TIM_CEN bit has been previously set by software. Trigger mode sets the TIM_CEN bit automatically through hardware. Bitname Bitfield Access Description |
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