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EM357-RTR Datasheet(PDF) 145 Page - Silicon Laboratories

Part # EM357-RTR
Description  High-Performance, Integrated ZigBee/802.15.4 System-on-Chip
PDF  241 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

EM357-RTR Datasheet(HTML) 145 Page - Silicon Laboratories

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145
Rev 1.3
9.5. Registers
Note:
Substitute “1” or “2” for “x” in the following detailed descriptions.
TIM1_CR1: Address: 0x4000E000 Reset: 0x0
TIM2_CR1: Address: 0x4000F000 Reset: 0x0
Register 9.1. TIMx_CR1
TIM1_CR1: Timer 1 Control Register 1
TIM2_CR1: Timer 2 Control Register 1
Bit
31
30
29
28
27
26
25
24
Name
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Name
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Name
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Name
TIM_ARBE
TIM_CMS
TIM_DIR
TIM_OPM
TIM_URS
TIM_UDIS
TIM_CEN
Bitname
Bitfield
Access
Description
TIM_ARBE
[7]
RW
Auto-Reload Buffer Enable.
0: TIMx_ARR register is not buffered.
1: TIMx_ARR register is buffered.
TIM_CMS
[6:5]
RW
Center-aligned Mode Selection.
00: Edge-aligned mode. The counter counts up or down depending on the direction bit
(TIM_DIR).
01: Center-aligned mode 1. The counter counts up and down alternatively.
Output compare interrupt flags of configured output channels (TIM_CCyS=00 in TIMx_C-
CMRy register) are set only when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternatively.
Output compare interrupt flags of configured output channels (TIM_CCyS=00 in TIMx_C-
CMRy register) are set only when the counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternatively.
Output compare interrupt flags of configured output channels (TIM_CCyS=00 in TIMx_C-
CMRy register) are set both when the counter is counting up or down.
Note:
Software may not switch from edge-aligned mode to center-aligned mode when
the counter is enabled (TIM_CEN = 1).
TIM_DIR
[4]
RW
Direction.
0: Counter used as up-counter.
1: Counter used as down-counter.
TIM_OPM
[3]
RW
One Pulse Mode.
0: Counter does not stop counting at the next UEV.
1: Counter stops counting at the next UEV (and clears the bit TIM_CEN).



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