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EM357-RTR Datasheet(PDF) 157 Page - Silicon Laboratories |
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EM357-RTR Datasheet(HTML) 157 Page - Silicon Laboratories |
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157 / 241 page  157 Rev 1.3 TIM1_CCMR2: Address: 0x4000E01C Reset: 0x0 TIM2_CCMR2: Address: 0x4000F01C Reset: 0x0 Timer channels can be programmed as inputs (capture mode) or outputs (compare mode). The direction of channel y is defined by TIM_CCyS in this register. The other bits in this register have different functions in input and in output modes. The TIM_OC* fields only apply to a channel configured as an output (TIM_CCyS = 0), and the TIM_IC* fields only apply to a channel configured as an input (TIM_CCyS > 0). Register 9.6. TIMx_CCMR2 TIM1_CCMR2: Timer 1 Capture/Compare Mode Register 2 TIM2_CCMR2: Timer 2 Capture/Compare Mode Register 2 Bit 31 30 29 28 27 26 25 24 Name 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Name 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name 0 TIM_OC4M TIM_OC4BE TIM_OC4FE TIM_CC4S TIM_IC4F TIM_IC4PSC Bit 7 6 5 4 3 2 1 0 Name 0 TIM_OC3M TIM_OC3BE TIM_OC3FE TIM_CC3S TIM_IC3F TIM_IC3PSC |
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