ADC1034 datasheet(11/18 Pages) NSC

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20 Functional Description (Continued)

occur there will be an uncertainty as to which SCLK rising

edge will clock in the first bit of data CS must remain low

during the complete IO exchange Also OE needs to be

low if data from the previous conversion needs to be ac-

cessed

231 CS LOW CONTINUOUSLY

Another way to accomplish synchronous serial communica-

tion is to tie CS low continuously and use SARS and SCLK to

synchronize the serial data exchange SCLK can be disabled

low during the conversion time and enabled after SARS

goes low With CS low during the conversion time a zero will

remain on DO until the conversion is completed Once the

conversion is complete the falling edge of SARS will shift

out on DO the MSB before SCLK is enabled This MSB

would be a leading zero if right-justified or D9 if left-justified

The rest of the data will be shifted out once SCLK is enabled

as discussed previously If CS goes high during the conver-

sion sequence DO is put into TRI-STATE and the conver-

sion result is not affected so long as CS remains high until

the end of the conversion

24 TYING SCLK and CCLK TOGETHER

SCLK and CCLK can be tied together The total conversion

time will increase because the maximum clock frequency is

now 1 MHz The timing diagrams and the serial IO ex-

change time (10 SCLK cycles) remain the same but the con-

version time (TC e 41 CCLK cycles) lengthens from a mini-

mum of 14 ms to a minimum of 41 ms In the case where CS

is low continuously since the applied clock cannot be dis-

abled SARS must be used to synchronize the data output

on DO and initiate a new conversion The falling edge of

SARS sends the MSB information out on DO The next ris-

ing edge of the clock shifts in MUX address bit A2 on DI

The following clock falling edge will clock the next data bit

of information out on DO A conversion will be started after

MUX addressing information has been loaded in (3 more

clocks) and the analog sampling time (45 clocks) has

elapsed The ADC1031 does not have SARS Therefore CS

cannot be left low continuously on the ADC1031

30 Analog Considerations

31 THE INPUT SAMPLE AND HOLD

The ADC103148’s samplehold capacitor is implemented

in its capacitive ladder structure After the channel address

is received the ladder is switched to sample the proper ana-

log input This sampling mode is maintained for 45 SCLK

cycles after the multiplexer addressing information is loaded

in For the ADC103148 the sampling of the analog input

starts on SCLK’s 4th rising edge

TLH10556 – 18

FIGURE 1 Analog Input Model

An acquisition window of 45 SCLK cycles is available to

allow the ladder capacitance to settle to the analog input

voltage Any change in the analog voltage before or after

the acquisition window will not effect the AD conversion

result

In the most simple case the ladder’s acquisition time is de-

termined by the Ron (9 kX) of the multiplexer switches the

CS1 (35 pF) and the total ladder (CL) and stray (CS2) capac-

itance (48 pF) For large source resistance the analog input

can be modeled as an RC network as shown in

Figure 1

The values shown yield an acquisition time of about 3 ms for

10 bit accuracy with a zero to a full scale change in the

reading External source resistance and capacitance will

lengthen the acquisition time and should be accounted for

The curve ‘‘Signal to Noise Ratio vs Output Frequency’’

(Figure 2) gives an indication of the usable bandwidth of the

ADC1031ADC1034ADC1038 The signal to noise ratio of

an ideal AD is the ratio of the RMS value of the full scale

input signal amplitude to the value of the total error ampli-

tude (including noise) caused by the transfer function of the

AD An ideal 10 bit AD converter with a total unadjusted

error of 0 LSB would have a signal to noise ratio of about

62 dB which can be derived from the equation

SN e 602(N) a 18

where SN is in dB and N is the number of bits

Figure 2

shows the signal to noise ratio vs input frequency of a typi-

cal ADC103148 with

LSB total unadjusted error The

dotted lines show signal-to-noise ratios for an ideal (noise-

less) 10 bit AD with 0 LSB error and an AD witha1LSB

error

The sample-and-hold error specifications are included in the

error and timing specifications of the AD The hold step

and gain error samplehold specs are taken into account in

the ADC103148’s total unadjusted error specification

while the hold settling time is included in the AD’s maxi-

mum conversion time specification The hold droop rate can

be thought of as being zero since an unlimited amount of

time can pass between a conversion and the reading of

data However once the data is read it is lost and another

conversion is started

32 INPUT FILTERING

Due to the sampling nature of the analog input transients

will appear on the input pins They are caused by the ladder

capacitance and internal stray capacitance charging current

flowing into VIN These transients will not degrade the AD’s

performance if they settle out within the sampling window

This will occur if external source resistance is kept to a mini-

mum

TLH10556 – 19

FIGURE 2 ADC103148 Signal to

Noise Ratio vs Input Frequency

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