AM652X datasheet(159/299 Pages) TI1

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AM6548, AM6528, AM6546

AM6526, AM6527

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SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Specifications

For more information, see section Networking Subsystem (NSS) in chapter Peripherals of the device TRM.

5.11.5.3 CSI2

NOTE

For more information, see the Camera Serial Interface 2 CAL Bridge chapter of the device

TRM

The camera adaptation layer (CAL) deals with the processing of the pixel data coming from an external

image sensor, data from memory. The CAL is a key component for the following multimedia applications:

camera viewfinder, video record, and still image capture. The CAL has two serial camera interfaces

(primary and secondary):

•

The primary serial interface (CSI2 Port) is compliant with MIPI CSI-2 protocol with four data lanes.

5.11.5.3.1 CSI-2 MIPI D-PHY

The CSI-2 port is compliant with the MIPI D-PHY RX specification v1.01.00 and the MIPI CSI-2

specification, with 4 data differential lanes plus 1 clock differential lane in synchronous mode, double data

rate:

•

1.5 Gbps (750 MHz) @OPP_NOM for each lane.

5.11.5.4 DDRSS

For more details about features and additional description information on the device DDR3L, DDR4, and

LPDDR4 Memory Interfaces, see the corresponding sections within Section 4.3, Signal Descriptions and

Section 6, Detailed Description.

The device has dedicated interfaces to DDR3L, DDR4, and LPDDR4 SDRAM. It supports JEDEC

JESD79-3-1, JESD79-4B, and JESD209-4B standards compliant DDR3L, DDR4, and LPDDR4 SDRAM

devices with the following features:

•

16-bit or 32-bit data path to external SDRAM memory

•

Memory device capacity: Up to 32 GB address space available over one chip select

5.11.5.5 DSS

For more details about features and additional description information on the device Display Subsystem –

Video Output Ports, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6,

Detailed Description.

Table 5-38, Table 5-39, Figure 5-34 and Figure 5-35 assume testing over the recommended operating

conditions and electrical characteristic conditions.

Table 5-38. DPI Video Output Switching Characteristics

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

tc(VOUT1_PCLK)

Cycle time, VOUT1_PCLK

6.06

tw(VOUT1_PCLKL)

Pulse duration, VOUT1_PCLK low

0.45×P(1)

tw(VOUT1_PCLKH)

Pulse duration, VOUT1_PCLK high

0.45×P(1)

td(VOUT1_PCLK-

VOUT_DATA)

Delay time, VOUT1_PCLK to VOUT1_DATA[23:0]

-0.68

1.78

td(VOUT1_PCLK-

VOUT_CTRL)

Delay time, VOUT1_PCLK to VOUT1_VSYNC, VOUT1_HSYNC,

VOUT1_DE

-0.68

1.78

AM652X Datasheet(PDF) 159 Page - Texas Instruments

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