 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AM652X Datasheet(PDF) 275 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
AM652X Datasheet(HTML) 275 Page - Texas Instruments |
|
|
275 / 299 page  275 AM6548, AM6528, AM6546 AM6526, AM6527 www.ti.com SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Detailed Description Copyright © 2017–2018, Texas Instruments Incorporated • Support for data safety mechanisms: – Bidirectional CRC on Multiple-SPI interface. – Handling ECC errors for flash devices with embedded correction engine. • Full integration with PHY module dedicated to more flexible and power efficient transfers. The following features are not supported on this family of devices: • OSPI1_D[7:4] are not pinned out. • OSPI1_SCn[3:2] are not pinned out. • DMA not supported. • Pulse events not used. • In Octal-SPI mode, Mode 1 and 2 are not supported. In Mode 3 DDR is not supported. • In Quad-SPI mode, Mode 1 and 2 are not supported. In Mode 3 DDR is not supported. For more information, see section Octal Serial Peripheral Interface (OSPI) in chapter Peripherals of the device TRM. 6.11.22 PCIE The Peripheral Component Interconnect Express (PCIe) subsystem is built around a multi-lane dual-mode PCIe controller that provides low pin-count, high reliability, and high-speed data transfers at rates of up to 8.0 Gbps per lane for serial links on backplanes and printed wiring boards. The device includes two instantiations of PCIe subsystem named PCIE0 and PCIE1. Each PCIe subsystem supports the following main features: The PCIe subsystems do not support the following features: • Compliance to PCIe® Base Specification, Revision 3.1 • One or two-lane configuration with up to 8.0 Gbps/lane (Gen3/Gen2) – PCIE0 used as 2-lane controller, configurable in 1x1 or 1x2 mode – PCIE1 used as 1-lane controller configured in 1x1 mode • Gen3 (8 Gbps 128/130-bit encoding), Gen2 (5 Gbps 8/10-bit encoding) and Gen1 (2.5 Gbps 8/10-bitb encoding) with auto-negotiation • Dynamic width conversion when switching between Gen1/2/3 modes • Root Complex (RC) or End Point (EP) operation modes • Maximum outbound payload size of 128 bytes • Maximum inbound payload size of 256 bytes • Maximum remote read request size of 4K bytes • Ultra-low transmit and receive latency • Automatic lane reversal as specified in the PCIe 3.0 specification (transmit and receive) • Polarity inversion on receive • One Physical Functions (PF), One Virtual Function (VF) • Single function in End Point (EP) mode • Four virtual channels (VC) • Four traffic classes (TC) • Automatic credit management • ECRC generation and checking • PCI Device Power Management states D0, D1, D3Hot and D3Cold with the exception of D3 cold with Vaux • PCIe Active State Power Management (ASPM) state L0s and L1 (with exceptions) • PCIe Link Power Management states, except L2 state |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Indian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
