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4

Analog Technologies

ATLS3A201D

Constant Current Laser Driver

To power GND

+5V

LIO

6

VPS 12

PGND

10

LIGD 8

LDA 9

GND

3

2.5VR

4

LIS

5

PGND 11

GND 7

LDGD

2

SDN

1

Laser Driver

A

K

Laser diode

D2

(Clock-wise)

S1 Shutdown

A

K

D1

LED

To DC voltmeter

To DC voltmeter

To signal GND

3

1 W1 10K

Figure 4.2. A Typical Stand-alone Application Schematic for ATLS3A201D-PD

Figure 4.1 and 4.2 shows a typical stand-alone application

circuit.

In Figure 4.1, the switch S1 is an external shut down switch,

it turns the driver off and on by tiding SDN pin to the

ground or releasing it respectively. In Figure 4.2, the switch

S1 is an external shut down switch, which turns the driver

off and on by tiding SDN pin to VPS or releasing it

respectively. The starting up time delay is about 4mS and

the shut down time is about 20µS.

The switch S1 can also be an electronic switch, such as an

I/O pin of a micro-driver, with an either open drain or

push/pull output. See Figure 5. For ATLS3A201D, the

internal equivalent circuit is a resistor of 10M pulling up this

pin to VPS rail. And for ATLS3A201D-PD, the internal

equivalent circuit is a resistor of 55k pulling down this pin

to GND. When this pin voltage is >1.4V, the driver is

enabled; <0.95V, the driver is shut down. Normal threshold

voltage = 1.2V.

If not using a switch (S1) to control the laser, leave the SDN

pin unconnected.

In Figure 4.1, the LED D1 is used to indicate laser diode

status. When LDGD pin is high, >2V, the laser diode control

loop is working properly. When LDGD pin is low, <0.3V,

the laser diode is bad, or there is a short or open circuit at

the laser diode. The LDGD pin can also be connected to a

digital input pin of a micro-driver, when software/firmware

is utilized in the system. See Figure 5. The equivalent circuit of

this pin is a 5k resistor pulling up it to the VPS rail and an open

drain FET pulling it down to the ground. The pull-up current

can be increased by connecting an external pull-up resistor

between VPS and LDGD pins, which is equivalent to

paralleling the external resistor with the internal 5k pull-up

resistor. However, the total pull-up resistor should be ≥1.5k @

drain FET cannot provide the resistors with enough pull-down

current to achieve a low enough potential level for a logic low

indication. To calculate the total pull-up resistor, use the

equation below:

where:

The laser diode D2 is connected between LDA and LDC. It is

worth mentioning that the power supply return terminal should

be connected to the pin 11 PGND and the cathode of the laser

diode should be connected to the pin 10 LDC. These 2 pins, 10

and 11, should not be connected together externally and they

are connected together internally already by the driver.

Figure 5 shows a typical micro-processor-based application

circuit.

To ADC & DAC

To ADC

To ADC

To micro-controller

To signal GND

To power GND

+5V

LIO

6

VPS 12

PGND

10

LIGD

8

LDA

9

GND

3

2.5VR

4

LIS

5

PGND 11

GND

7

LDGD

2

SDN

1

Laser Driver

To DAC

To signal GND

To micro-controller

A

K

Laser diode

D2

Figure 5. A Typical Micro-processor-based Application Schematic

LDC

+5V