P0111MA2AL3 datasheet(4/9 Pages) STMICROELECTRONICS

4 / 9 page

Characteristics

P011xx

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Figure 5.

Relative variation of gate trigger,

holding and latching current versus

junction temperature

Figure 6.

Relative variation of holding

current versus gate-cathode

resistance (typical values)

-40

-20

100

120

140

T (°C)

I,I ,I [T ] /

GT H L

,I ,I [T =25°C]

GT H L

IGT

IH & I

= 1k

typical values

1E-2

1E-1

1E+0

1E+1

R(k )

I [R

] / I [

=1k ]

HGK

RGK

Tj = 25°C

Figure 7.

Relative variation of dV/dt immunity

versus gate-cathode resistance

(typical values).

Figure 8.

Relative variation of dV/dt immunity

versus gate-cathode capacitance

(typical values)

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

0.1

1.0

10.0

R(k )

dV/dt[R

] / dV/dt[

=1k ]

RGK

Tj = 125°C

V = 0.67 x V

DRM

0123

4567

(nF)

dV/dt[C

] / dV/dt[

=1k ]

RGK

V = 0.67 x V

= 125°C

= 1k

DRM

Figure 9.

Surge peak on-state current versus

number of cycles

Figure 10.

Non-repetitive surge peak on-state

current and corresponding value

of I²t

(A)

TSM

100

1000

Number of cycles

Non repetitive

T initial=25°C

Repetitive

=25°C

amb

t =10ms

One cycle

(A), I t (A s)

TSM

100.0

10.0

1.0

0.1

0.01

0.10

1.00

10.00

T initial = 25°C

I t

ITSM

t (ms)

sinusoidal pulse with

width t < 10ms

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