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WM8987LGECO/RV Datasheet(PDF) 12 Page - Wolfson Microelectronics plc |
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WM8987LGECO/RV Datasheet(HTML) 12 Page - Wolfson Microelectronics plc |
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12 / 58 page  WM8987L Pre-Production w PP Rev 3.0 January 2007 12 Test Conditions DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25 oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Bit Clock Timing Information BCLK rise time (10pF load) tBCLKR 3 ns BCLK fall time (10pF load) tBCLKF 3 ns BCLK duty cycle (normal mode, BCLK = MCLK/n) tBCLKDS 50:50 BCLK duty cycle (USB mode, BCLK = MCLK) tBCLKDS TMCLKDS Audio Data Input Timing Information ADCLRC/DACLRC propagation delay from BCLK falling edge tDL 10 ns ADCDAT propagation delay from BCLK falling edge tDDA 40 ns DACDAT setup time to BCLK rising edge tDST 10 ns DACDAT hold time from BCLK rising edge tDHT 10 ns AUDIO INTERFACE TIMING – SLAVE MODE BCLK DACLRC/ ADCLRC t BCH t BCL t BCY DACDAT ADCDAT t LRSU t DS t LRH t DH t DD Figure 3 Digital Audio Data Timing – Slave Mode Test Conditions DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25 oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY 50 ns BCLK pulse width high tBCH 20 ns BCLK pulse width low tBCL 20 ns ADCLRC/DACLRC set-up time to BCLK rising edge tLRSU 10 ns ADCLRC/DACLRC hold time from BCLK rising edge tLRH 10 ns DACDAT hold time from BCLK rising edge tDH 10 ns ADCDAT propagation delay from BCLK falling edge tDD 10 ns Note: BCLK period should always be greater than or equal to MCLK period. |
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