MCP1725 datasheet(22/32 Pages) MICROCHIP

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MCP1725

DS22026A-page 22

5.3.2

JUNCTION TEMPERATURE

ESTIMATE

To estimate the internal junction temperature, the

calculated temperature rise is added to the ambient or

offset temperature. For this example, the worst-case

junction temperature is estimated below:

As you can see from the result, this application will be

operating near around a junction temperature of

100°C. The PCB layout for this application is very

important as it has a significant impact on the junction-

to-ambient thermal resistance (R

θJA) of the 2x3 DFN

package, which is very important in this application.

5.3.3

MAXIMUM PACKAGE POWER

DISSIPATION AT 60°C AMBIENT

TEMPERATURE

From this table, you can see the difference in maximum

allowable power dissipation between the 2x3 DFN

package and the 8-pin SOIC package. This difference

is due to the exposed metal tab on the bottom of the

DFN package. The exposed tab of the DFN package

provides a very good thermal path from the die of the

LDO to the PCB. The PCB then acts like a heatsink,

providing more area to distribute the heat generated by

the LDO.

5.4

CDELAY Calculations (typical)

TJ =TJRISE + TA(MAX)

TJ = 38.8°C + 60.0°C

TJ = 98.8°C

2x3 DFN (76° C/W R

θJA):

PD(MAX) = (125°C – 60°C) / 76° C/W

PD(MAX) = 0.855W

SOIC8 (163°C/Watt R

θJA):

PD(MAX) = (125°C – 60°C)/ 163° C/W

PD(MAX) = 0.399W

ΔT

ΔV

-------

•

Where:

C=CDELAY Capacitor

I=CDELAY charging current,

140 nA typical.

ΔT

time delay

ΔV=CDELAY threshold voltage,

0.42V typical

ΔT

ΔV

-------

•

140nA

ΔT

•

()

0.42V

----------------------------------

333.3

–

×10

ΔT

•

For a delay of 300ms,

C = 333.3E-09 *.300

C = 100E-09 µF (0.1 µF)

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