SC4612STRT datasheet(14/24 Pages) SEMTECH

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 2007 Semtech Corp.

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SC4612

POWER MANAGEMENT

PCB LAYOUT GUIDELINES

Careful attention to layout is necessary for successful

implementation of the SC4612 PWM controller. High

switching currents are present in the application and their

effect on ground plane voltage differentials must be

understood and minimized.

1) The high power section of the circuit should be laid out

first. A ground plane should be used. The number and

position of ground plane interruptions should not

unnecessarily compromise ground plane integrity. Isolated

or semi-isolated areas of the ground plane may be

deliberately introduced to constrain ground currents to

particular areas; for example, the input capacitor and

bottom FET ground.

2) The loop formed by the Input Capacitor(s) (Cin), the Top

FET (M1), and the Bottom FET (M2) must be kept as small

as possible. This loop contains all the high current, fast

transition switching. Connections should be as wide and

as short as possible to minimize loop inductance.

Minimizing this loop area will a) reduce EMI, b) lower ground

injection currents, resulting in electrically “cleaner” grounds

for the rest of the system and c) minimize source ringing,

resulting in more reliable gate switching signals.

3) The connection between the junction of M1, M2 and

the output inductor should be a wide trace or copper region.

It should be as short as practical. Since this connection

has fast voltage transitions, keeping this connection short

will minimize EMI. Also keep the Phase connection to the

IC short. Top FET gate charge currents flow in this trace.

4) The Output Capacitor(s) (Cout) should be located as

close to the load as possible. Fast transient load currents

are supplied by Cout only, and therefore, connections

between Cout and the load must be short, wide copper

areas to minimize inductance and resistance.

5) The SC4612 is best placed over a quiet ground plane

area. Avoid pulse currents in the Cin, M1, M2 loop flowing

in this area. GND should be returned to the ground plane

close to the package and close to the ground side of (one

of) the output capacitor(s). If this is not possible, the GND

pin may be connected to the ground path between the

Output Capacitor(s) and the Cin, M1, M2 loop. Under no

circumstances should GND be returned to a ground inside

the Cin, M1, M2 loop.

6) Allow adequate heat sinking area for the power

components. If multiple layers will be used, provide

sufficent vias for heat transfer

Application Information (Cont.)

Voltage and current waveforms of buck power stage .

Vout

VIN

Ids (Top Fet)

Ids (Bottom Fet)

I (Input Capacitor)

Vphase

I (Inductor)

Vout

I (Output Capacitor)

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