LSM303DLHCTR datasheet(26/42 Pages) STMICROELECTRONICS

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LSM303DLHC

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Doc ID 018771 Rev 1

7.1.4

CTRL_REG4_A (23h)

7.1.5

CTRL_REG5_A (24h)

Table 25.

CTRL_REG3_A description

I1_CLICK

CLICK interrupt on INT1. Default value 0.

(0: disable, 1: enable)

I1_AOI1

AOI1 interrupt on INT1. Default value 0.

(0: disable, 1: enable)

I1_AOI2

AOI2 interrupt on INT1. Default value 0.

(0: disable, 1: enable)

I1_DRDY1

DRDY1 interrupt on INT1. Default value 0.

(0: disable, 1: enable)

I1_DRDY2

DRDY2 interrupt on INT1. Default value 0.

(0: disable, 1: enable)

I1_WTM

FIFO watermark interrupt on INT1. Default value 0.

(0: disable, 1: enable)

I1_OVERRUN

FIFO overrun interrupt on INT1. Default value 0.

(0: disable, 1: enable)

Table 26.

CTRL_REG4_A register

BDU

BLE

FS1

FS0

0(1)

This bit must be set to ‘0’ for correct working of the device.

0(1)

SIM

Table 27.

CTRL_REG4_A description

BDU

Block data update. Default value: 0

(0: continuos update, 1: output registers not updated until MSB and LSB

reading

BLE

Big/little endian data selection. Default value 0.

(0: data LSB @ lower address, 1: data MSB @ lower address)

FS1-FS0

Full-scale selection. Default value: 00

(00: +/- 2G, 01: +/- 4G, 10: +/- 8G, 11: +/- 16G)

High resolution output mode: Default value: 0

(0: high resolution disable, 1: high resolution enable)

SIM

SPI serial interface mode selection. Default value: 0

(0: 4-wire interface, 1: 3-wire interface).

Table 28.

CTRL_REG5_A register

BOOT

FIFO_EN

LIR_INT1

D4D_INT1

LIR_INT2

D4D_INT2

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