ICS83021I datasheet(4/12 Pages) IDT

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ICS83021I

1-TO-1 DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR

IDT™ / ICS™ LVCMOS/LVTTL TRANSLATOR

ICS83031AMI REV. C OCTOBER 31, 2008

AC Electrical Characteristics

Table 4A. AC Characteristics, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the

device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after

thermal equilibrium has been reached under these conditions.

All parameters measured at fMAX unless noted otherwise.

NOTE 1: Measured from the differential input crossing point to the output at VDD/2.

NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.

Using the same type of inputs on each device, the outputs are measured at VDD/2.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

Table 4B. AC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the

device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after

thermal equilibrium has been reached under these conditions.

All parameters measured at fMAX unless noted otherwise.

NOTE 1: Measured from the differential input crossing point to the output at VDD/2.

NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.

Using the same type of inputs on each device, the outputs are measured at VDD/2.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

Parameter

Symbol

Test Conditions

Minimum

Typical

Maximum

Units

fMAX

Output Frequency

350

MHz

tPD

Propagation Delay, NOTE 1

≤ 350MHz

1.7

2.0

2.3

tsk(pp)

Part-to-Part Skew; NOTE 2, 3

500

tjit

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section

100MHz, Integration Range

(637kHz – 10MHz)

0.21

tR / tF

Output Rise/Fall Time

0.8V to 2V

100

250

400

odc

Output Duty Cycle

≤ 166MHz

166MHz < ƒ

≤ 350MHz

Parameter

Symbol

Test Conditions

Minimum

Typical

Maximum

Units

fMAX

Output Frequency

350

MHz

tPD

Propagation Delay, NOTE 1

≤ 350MHz

1.9

2.2

2.5

tsk(pp)

Part-to-Part Skew; NOTE 2, 3

500

tjit

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section

100MHz, Integration Range

(637kHz – 10MHz)

0.21

tR / tF

Output Rise/Fall Time

20% to 80%

250

550

odc

Output Duty Cycle

≤ 250MHz

250MHz < ƒ

≤ 350MHz

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