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LQFP64 Datasheet(PDF) 64 Page - STMicroelectronics

Part # LQFP64
Description  Low-density access line, ARM-based 32-bit MCU with 16 or 32 KB Flash, 5 timers, ADC and 4 communication interfaces
PDF  79 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

LQFP64 Datasheet(HTML) 64 Page - STMicroelectronics

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Electrical characteristics
STM32F101x4, STM32F101x6
64/79
Doc ID 15058 Rev 5
5.3.17
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 42 are derived from tests
performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 8.
Note:
It is recommended to perform a calibration after each power-up.
Table 42.
ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
Power supply
2.4
3.6
V
fADC
ADC clock frequency
0.6
14
MHz
fS
(1)
Sampling rate
0.05
1
MHz
fTRIG
(1)
External trigger frequency
fADC = 14 MHz
823
kHz
17
1/fADC
VAIN
Conversion voltage range(2)
0 (VSSA or VREF-
tied to ground)
VREF+
V
RAIN
(1)
External input impedance
See Equation 1 and
Table 43 for details
50
k
Ω
RADC
(1)
Sampling switch resistance
1
k
Ω
CADC
(1)
Internal sample and hold
capacitor
8pF
tCAL
(1)
Calibration time
fADC = 14 MHz
5.9
µs
83
1/fADC
tlat
(1)
Injection trigger conversion
latency
fADC = MHz
0.214
µs
3(3)
1/fADC
tlatr
(1)
Regular trigger conversion
latency
fADC = 14 MHz
0.143
µs
2(3)
1/fADC
tS
(1)
Sampling time
fADC = 14 MHz
0.107
17.1
µs
1.5
239.5
1/fADC
tSTAB
(1)
Power-up time
0
0
1
µs
tCONV
(1)
Total conversion time
(including sampling time)
fADC = 14 MHz
1
18
µs
14 to 252 (tS for sampling +12.5 for
successive approximation)
1/fADC
1.
Guaranteed by design, not tested in production.
2.
VREF+ is internally connected to VDDA and VREF- is be internally connected to VSSA.
3.
For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 42.



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