2 Register map

Migrating applications from ST7FLITE1x to ST7FLITE1xB

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2

Register map

In ST7FLITE1xB, some register addresses have been added, some modified to add new

features and peripherals.

Note:

For easy software migration, two general rules to be followed:

All “reserved” byte memory areas must never be “read” or “write”.

All “reserved” and “unused” bits must be left unchanged when accessing the byte.

2.1

Register address

These changes are classified in two groups:

1.

New features added: Port C, dual counters in ART Timer, one pulse mode, External Break,

Dead Time generation, Force Update in ART Timer, Analog Comparator and PLL divider.

2.

TRANCR (Transfer Control Register) has been replaced by ATCSR2 (Timer Control

Register2). Seven bits relative to the new features in ART Timer have been added in

ATCSR2 register. TRAN <bit0> of TRANCR register has been replaced by TRAN1 <bit0>.

Please, refer to the datasheet for the detailed description of the new features.