PIC16F628-20SLASHSS datasheet(65/160 Pages) MICROCHIP

65 / 160 page

PIC16F62X

Preliminary

DS40300B-page 65

10.2

Compare Mode

In Compare mode, the 16-bit CCPR1 register value is

constantly compared against the TMR1 register pair

value. When a match occurs, the RB3/CCP1 pin is:

• driven High

• driven Low

• remains Unchanged

The action on the pin is based on the value of control

bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the

same time, interrupt flag bit CCP1IF is set.

FIGURE 10-2: COMPARE MODE

OPERATION BLOCK

DIAGRAM

10.2.1

CCP PIN CONFIGURATION

The user must configure the RB3/CCP1 pin as an out-

put by clearing the TRISB<3> bit.

10.2.2

TIMER1 MODE SELECTION

Timer1 must be running in Timer mode or Synchro-

nized Counter mode if the CCP module is using the

compare feature. In Asynchronous Counter mode, the

compare operation may not work.

10.2.3

SOFTWARE INTERRUPT MODE

When generate software interrupt is chosen the CCP1

pin is not affected. Only a CCP interrupt is generated (if

enabled).

10.2.4

SPECIAL EVENT TRIGGER

In this mode, an internal hardware trigger is generated

which may be used to initiate an action.

The special event trigger output of CCP1 resets the

TMR1 register pair. This allows the CCPR1 register to

effectively be a 16-bit programmable period register for

Timer1.

TABLE 10-2

REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1

CCPR1H CCPR1L

TMR1H

TMR1L

Comparator

Output

Logic

Special Event Trigger (CCP2 only)

Set flag bit CCP1IF

(PIR1<2>)

match

RB3/CCP1

TRISB<3>

CCP1CON<3:0>

Mode Select

Output Enable

Special event trigger will reset Timer1, but not

set interrupt flag bit TMR1IF (PIR1<0>)

Note:

Clearing the CCP1CON register will force

the RB3/CCP1 compare output latch to the

default low level. This is not the data latch.

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR

Value on

all other

resets

0Bh/8Bh/1

0Bh/18Bh

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x 0000 000u

0Ch

PIR1

EEIF

CMIF

RCIF

TXIF

—CCP1IF

TMR2IF

TMR1IF

0000 -000 0000 -000

8Ch

PIE1

EEIE

CMIF

RCIE

TXIE

—

CCP1IE

TMR2IE

TMR1IE 0000 -000 0000 -000

87h

TRISB

PORTB Data Direction Register

1111 1111 1111 1111

0Eh

TMR1L

Holding register for the Least Significant Byte of the 16-bit TMR1 register

xxxx xxxx uuuu uuuu

0Fh

TMR1H

Holding register for the Most Significant Byte of the 16-bit TMR1register

xxxx xxxx uuuu uuuu

10h

T1CON

—

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

15h

CCPR1L

Capture/Compare/PWM register1 (LSB)

xxxx xxxx uuuu uuuu

16h

CCPR1H

Capture/Compare/PWM register1 (MSB)

xxxx xxxx uuuu uuuu

17h

CCP1CON

—

CCP1X

CCP1Y

CCP1M3

CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

Legend:

= unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by Capture and Timer1.

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