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EM357-RTR Datasheet(PDF) 152 Page - Silicon Laboratories |
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EM357-RTR Datasheet(HTML) 152 Page - Silicon Laboratories |
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152 / 241 page  Rev 1.3 152 TIM_CC2G [2] W Capture/Compare 2 Generation. 0: Does nothing. 1: If CC2 configured as output channel: The TIM_CC2IF flag is set. If CC2 configured as input channel: The TIM_CC2IF flag is set. The INT_TIMMISSCC2IF flag is set if the TIM_CC2IF flag was already high. The current value of the counter is captured in TMRx_CCR2 register. TIM_CC1G [1] W Capture/Compare 1 Generation. 0: Does nothing. 1: If CC1 configured as output channel: The TIM_CC1IF flag is set. If CC1 configured as input channel: The TIM_CC1IF flag is set. The INT_TIMMISSCC1IF flag is set if the TIM_CC1IF flag was already high. The current value of the counter is captured in TMRx_CCR1 register. TIM_UG [0] W Update Generation. 0: Does nothing. 1: Re-initializes the counter and generates an update of the registers. This also clears the prescaler counter but the prescaler ratio is not affected. The counter is cleared if center-aligned mode is selected or if TIM_DIR=0 (up-counting), other- wise it takes the auto-reload value (TMR1_ARR) if TIM_DIR=1 (down-counting). Bitname Bitfield Access Description |
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