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MP2014 Datasheet(PDF) 8 Page - Monolithic Power Systems |
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MP2014 Datasheet(HTML) 8 Page - Monolithic Power Systems |
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8 / 13 page ![]() MP2014 - 40V, 500mA, LOW QUIESCENT CURRENT LINEAR REGULATOR MP2014 Rev. 1.01 www.MonolithicPower.com 8 1/15/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. OPERATION The MP2014 is a linear regulator that supplies power to systems with high voltage batteries. It includes a wide 3V to 40V input range, low dropout voltage and low quiescent supply current. The MP2014 provides wide variety of fixed output voltage options: 1.8V, 1.9V, 2.3V, 2.5V, 3.0V, 3.3V, 3.45V, 5.0V. Short-Circuit Protection The regulator output current is internally limited and the device is protected against short-circuit, over-load. The peak output current is limited to around 900mA, which exceeds the 500mA recommended continuous output current. Thermal Shutdown When the junction temperature exceeds the upper threshold (165 °C), the thermal sensor sends a signal to the control logic to shutdown the IC. The IC will restart when the temperature has sufficiently cooled (135 °C). The maximum power output current is a function of the package’s maximum power dissipation for a given temperature. The maximum power dissipation is dependent on the thermal resistance of the case and the circuit board, the temperature difference between the die junction and the ambient air, and the rate of air flow. The GND pin and Exposed Pad must be connected to the ground plane for proper dissipation. Power Good Output MP2014 has one power good (PG) pin. The PG pin is the open drain of an internal MOSFET. It should be connected to VOUT or external voltage source(<15V) through a resistor (i.e. 100kohm). After the VOUT reaches 93% of nominal value, the MOSFET turns off and PG pin is pulled to high by VOUT or external voltage source. When the VOUT drops to 88% of nominal value, the PG voltage is pulled to GND. There is a delay time when PG asserts high. The delay time can be programmed by adding a capacitor on PGDL. To select a capacitor for PGDL, use below equation: PGDL PGDL PGDL th_PGDL t(ms) I ( A) C(nF) V(V) μ × = Where tPGDL is the desired delay time for PG asserts high, IPGDL is the PGDL charging current and Vth_PGDL is 1.65V. Figure 2 shows the power good timing. Figure 1: Functional Block Diagram |
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