FS98O02B-PCE datasheet(33/50 Pages) FORTUNE

33 / 50 page

FS98O02

Rev.1.5

33/50

Table 16-7: FTB selection table

SFT[2]

FTB

ADC Low Pass Filter is disabled

ADC Low Pass Filter is enabled

Table 16-8: INH selection table

SFT[0]

INH (ADC positive input port signal)

FTB

FTIN

Set SINL[1:0] to decide the ADC negative input port signal. (Table 16-9)

Table 16-9: INL selection table

SINL[1:0]

INL for FS98O02A / B

INL for FS98O02C

AD2

AD3

VRRL

AD3

LVDL

Set ADG[1:0] to decide the ADC input gain. (Table 16-10)

Table 16-10: ADG selection table

ADG[1:0]

ADC input gain

2/3

7/3

Set SVRH[1:0] to decide the ADC reference voltage positive input port signal. (Table 16-11)

Table 16-11: VRH selection table

SVRH[1:0]

VRH (ADC reference voltage positive input)

AD4

VRRH

Set SVRL[1:0] to decide the ADC reference voltage negative input port signal. (Table 16-12)

Table 16-12: VRL selection table

SVRL[1:0]

VRL for FS98O02A / B

VRL for FS98O02C

AGND

AD3

VRRL

AD3

VRRL

AD3

10.

Set ADIE and GIE register flags to enable the ADC interrupt

11.

Set ADEN register flag, the embedded

Σ-Δ modulator will be enabled.

12.

Set ADRST register flag, the comb filter will be enabled.

13.

When the ADC interrupt happen, read the ADO[23:8] to get the ADC output.(ADO[23:22] are signed bits)

1 The input of ADC Low Pass Filter is FTIN, and the output is FTB

FS98O02B-PCE Datasheet(PDF) 33 Page - Fortune Semiconductor Corp.

FS98O02B-PCE Datasheet(HTML) 33 Page - Fortune Semiconductor Corp.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Datasheet Download

Link URL