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AM6548 Datasheet(PDF) 66 Page - Texas Instruments |
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AM6548 Datasheet(HTML) 66 Page - Texas Instruments |
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66 / 282 page  Table 6-8. DDRSS0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] DDR_VTP DDRSS Calibration Resistor (2) A F13 (1) This pin is intended for observation purpose only. No external voltage should be applied to this pin. (2) An external 240Ω ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin. (3) Do not connect any signal, test point, or board trace to this signal. 6.3.4.2 DDRSS Mapping Table 6-9 presents DDRSS interface signal mapping per device memory type. Note DDR3L and LPDDR4 memory types are not supported on this SoC. Table 6-9. DDRSS Signal Mapping SIGNAL NAME [1] MEMORY TYPE PIN TYPE[3] BALL[4] DDR3L(2) DDR4(1) (2) LPDDR4(1) DDR_AC0 A0 A0 CA0_A IO A10 DDR_AC1 A1 A1 CA1_A IO D9 DDR_AC2 A2 A2 CA2_A IO C9 DDR_AC3 A3 A3 CA3_A IO E9 DDR_AC4 A4 A4 CA4_A IO A9 DDR_AC5 A5 A5 CA5_A IO E8 DDR_AC6 A6 A6 CA0_B IO F8 DDR_AC7 A7 A7 CA1_B IO C7 DDR_AC8 A8 A8 CA2_B IO C8 DDR_AC9 A9 A9 CA3_B IO D7 DDR_AC10 A10 A10 CA4_B IO E7 DDR_AC11 A11 A11 CA5_B IO A6 DDR_AC12 A12 A12 CS0_B IO F7 DDR_AC13 A13 A13 CKE0_B IO D6 DDR_AC14 A14 A14/WE_n CS1_B IO C6 DDR_AC15 A15 A15/CAS_n CKE1_B IO F6 DDR_AC16 WE_n A16/RAS_n IO E6 DDR_AC17 CAS_n A17 IO E5 DDR_AC18 RAS_n ACT_n IO D8 DDR_AC19 BA0 BA0 IO D10 DDR_AC20 BA1 BA1 IO E10 DDR_AC21 BA2 BG0 IO C10 DDR_AC22 BG1 IO F11 DDR_AC23 PAR IO B10 DDR_AC24 CS0_n CS0_n CS0_A IO D11 DDR_AC25 ODT0 ODT0 IO B11 DDR_AC26 CKE0 CKE0 CKE0_A IO C11 DDR_AC27 CS1_n CS1_n CS1_A IO E11 DDR_AC28 ODT1 ODT1 IO E12 DDR_AC29 CKE1 CKE1 CKE1_A IO D12 DDR_ALERTn ALERT_n IO D5 DDR_CK0P CK0 CK0_t CK_t_A IO A8 AM6548, AM6528, AM6526 SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021 www.ti.com 66 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AM6548 AM6528 AM6526 |
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