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AM6548BACDXEAF Datasheet(PDF) 214 Page - Texas Instruments |
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AM6548BACDXEAF Datasheet(HTML) 214 Page - Texas Instruments |
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214 / 282 page  Table 7-52. MMC DLL Delay Mapping for All Timing Modes (continued) REGISTER NAME MMCSDn_SS_PHY_CTRL_4_REG MMCSDn_SS_PHY_CTRL_5_REG BIT FIELD [27:24] [20] [15:12] [8] [4:0] [17:16] [9:8]] [2:0] BIT FIELD NAME STRBSE L OTAPDLYEN A OTAPDLYSE L ITAPDLYEN A ITAPDLYS EL SELDLYTXCL K SELDLYRXCL K SEL100 SEL50 CLKBUFS EL MODE DESCRIPTIO N STROBE DELAY OUTPUT DELAY ENABLE OUTPUT DELAY VALUE INPUT DELAY ENABLE INPUT DELAY VALUE DLL DELAY CHAIN SELECT DLL REF FREQUEN CY DELAY BUFFER DURATIO N SDR104 4- or 8-bit PHY operating 1.8 V, SD/SDIO 200 MHz 0x0 0x1 0x7 0x1 Tuning 0x0 0x0 0x7 HS200 4- or 8-bit PHY operating 1.8 V, JEDEC 200 MHz 0x0 0x1 0x5 0x1 Tuning 0x0 0x0 0x7 For more information, see section Multimedia Card/Secure Digital (eMMC/SD/SDIO) Interface in the device TRM. 7.9.5.16.1.1 Default Speed, 3.3V Legacy SDR Mode Table 7-53 and Table 7-54 present Timing requirements and Switching characteristics for MMCi - Default Speed, 3.3V Legacy SDR in receiver and transmitter mode (see Figure 7-72 and Figure 7-73) Table 7-53. Timing Requirements for MMCi - Default Speed Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT DSSD5 tsu(cmdV-clkH) Setup time, MMCi_CMD valid before MMCi_CLK rising clock edge 2.15 ns DSSD6 th(clkH-cmdV) Hold time, MMCi_CMD valid after MMCi_CLK rising clock edge 19.67 ns DSSD7 tsu(dV-clkH) Setup time, MMCi_DAT[j:0] valid before MMCi_CLK rising clock edge 2.15 ns DSSD8 th(clkH-dV) Hold time, MMCi_DAT[j:0] valid after MMCi_CLK rising clock edge 19.67 ns Table 7-54. Switching Characteristics for MMCi - Default Speed Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT DSSD0 fop(clk) Operating frequency, MMCi_CLK 25 MHz DSSD1 tw(clkH) Pulse duration, MMCi_CLK high 18.7 ns DSSD2 tw(clkL) Pulse duration, MMCi_CLK low 18.7 ns DSSD3 td(clkL-cmdV) Delay time, MMCi_CLK falling clock edge to MMCi_CMD transition -14.1 14.1 ns DSSD4 td(clkL-dV) Delay time, MMCi_CLK falling clock edge to MMCi_DAT[j:0] transition -14.1 14.1 ns AM6548, AM6528, AM6526 SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021 www.ti.com 214 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AM6548 AM6528 AM6526 |
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