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AM6548BACDXEAF Datasheet(PDF) 218 Page - Texas Instruments |
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AM6548BACDXEAF Datasheet(HTML) 218 Page - Texas Instruments |
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218 / 282 page  MMC[ ]_CLK x MMC CMD [ ]_ x MMC DAT [ _ [3:0] x] SDR255 SDR257 SDR256 SDR258 SDR259 SDR258 SDR259 Figure 7-79. eMMC/SD/SDIO in - SDR25, 1.8-V High-Speed SDR - Transmitter Mode 7.9.5.16.1.5 UHS-I DDR50 Mode Table 7-61 and Table 7-62 present Timing requirements and Switching characteristics for MMCi - DDR50, 1.8-V and 3.3-V High-Speed DDR in receiver and transmitter mode (see Figure 7-80 and Figure 7-81). Table 7-61. MMCi - 1.8-V, 3.3-V High-Speed DDR Timing Requirements NO.(1) PARAMETER(2) MIN MAX UNIT DDR505 tsu(cmdV-clkH) Setup time, MMCi_CMD valid before MMCi_CLK rising clock edge 8.08 ns DDR506 th(clkH-cmdV) Hold time, MMCi_CMD valid after MMCi_CLK rising clock edge 1.99 ns DDR507 tsu(dV-clk) Setup time, MMCi_DAT[j:0] valid before MMCi_CLK transition 2.59 ns DDR508 th(clk-dV) Hold time, MMCi_DAT[j:0] valid after MMCi_CLK transition 1.75 ns (1) j in [j:0] is equal to 7 (for MMC0). (2) Timing requirements for 50 MHz DDR is only applicable when interfacing with JEDEC eMMC devices. Tuning should be done if interfacing to SD/SDIO devices. Table 7-62. MMCi - DDR50, 1.8-V/3.3-V High-Speed DDR Switching Characteristics NO. PARAMETER DESCRIPTION MIN MAX UNIT DDR500 fop(clk) Operating frequency, MMCi_CLK 40 MHz DDR501 tw(clkH) Pulse duration, MMCi_CLK high 11.58 ns DDR502 tw(clkL) Pulse duration, MMCi_CLK low 11.58 ns DDR503 td(clk-cmdV) Delay time, MMCi_CLK rising clock edge to MMCi_CMD transition 3.32 18.06 ns DDR504 td(clk-dV) Delay time, MMCi_CLK transition to MMCi_DAT[j:0] transition 2.82 8.87 ns Figure 7-80. eMMC/SD/SDIO - High-Speed DDR - Receive Mode AM6548, AM6528, AM6526 SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021 www.ti.com 218 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AM6548 AM6528 AM6526 |
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