AM6548BACDXEAF datasheet(215/282 Pages) TI

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Figure 7-72. eMMC/SD/SDIO in - Default Speed - Receiver Mode

Figure 7-73. eMMC/SD/SDIO in - Default Speed - Transmitter Mode

7.9.5.16.1.2 High Speed, 3.3V High Speed SDR Mode

Table 7-55 and Table 7-56 present Timing requirements and Switching characteristics for MMCi - High Speed

and 3.3V High Speed SDR in receiver and transmitter mode (see Figure 7-74 and Figure 7-75).

Table 7-55. Timing Requirements for MMCi - High Speed Mode

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

HSSD3

tsu(cmdV-clkH)

Setup time, MMCi_CMD valid before MMCi_CLK rising clock edge

2.91

HSSD4

th(clkH-cmdV)

Hold time, MMCi_CMD valid after MMCi_CLK rising clock edge

2.76

HSSD7

tsu(dV-clkH)

Setup time, MMCi_DAT[j:0] valid before MMCi_CLK rising clock edge

2.91

HSSD8

th(clkH-dV)

Hold time, MMCi_DAT[j:0] valid after MMCi_CLK rising clock edge

2.76

Table 7-56. Switching Characteristics for MMCi - High Speed Mode

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

HSSD1

fop(clk)

Operating frequency, MMCi_CLK

MHz

HSSD2H

tw(clkH)

Pulse duration, MMCi_CLK high

9.2

HSSD2L

tw(clkL)

Pulse duration, MMCi_CLK low

9.2

HSSD5

td(clkL-cmdV)

Delay time, MMCi_CLK falling clock edge to MMCi_CMD transition

-6.44

3.44

HSSD6

td(clkL-dV)

Delay time, MMCi_CLK falling clock edge to MMCi_DAT[j:0]

transition

-6.44

3.44

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AM6548, AM6528, AM6526

SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021

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