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AM6548BACDXEAF Datasheet(PDF) 217 Page - Texas Instruments |
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AM6548BACDXEAF Datasheet(HTML) 217 Page - Texas Instruments |
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217 / 282 page  MMC[ ]_CMD x MMC DAT [ ]_ [3:0] x SDR121 SDR122 SDR123 SDR124 MMC[ ]_CLK x Figure 7-76. eMMC/SD/SDIO in - SDR12, 1.8-V Legacy SDR - Receiver Mode MMC[ ]_CLK x MMC CMD [ ]_ x MMC DAT [ ]_ [3:0] x SDR125 SDR127 SDR126 SDR128 SDR129 SDR128 SDR129 Figure 7-77. eMMC/SD/SDIO in - SDR12, 1.8-V Legacy SDR - Transmitter Mode 7.9.5.16.1.4 UHS-I SDR25 Mode Table 7-59 and Table 7-60 present Timing requirements and Switching characteristics for MMCi - SDR25, 1.8V High Speed SDR in receiver and transmitter mode (see Figure 7-78 and Figure 7-79). Table 7-59. Timing Requirements for MMCi - SDR25, 1.8-V High-Speed SDR Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT SDR251 tsu(cmdV-clkH) Setup time, MMCi_CMD valid before MMCi_CLK rising clock edge 2.9 ns SDR252 th(clkH-cmdV) Hold time, MMCi_CMD valid after MMCi_CLK rising clock edge 1.75 ns SDR253 tsu(dV-clkH) Setup time, MMCi_DAT[j:0] valid before MMCi_CLK rising clock edge 2.9 ns SDR254 th(clkH-dV) Hold time, MMCi_DAT[j:0] valid after MMCi_CLK rising clock edge 1.75 ns Table 7-60. Switching Characteristics for MMCi - SDR25, 1.8-V High-Speed SDR Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT SDR255 fop(clk) Operating frequency, MMCi_CLK 50 MHz SDR256 tw(clkH) Pulse duration, MMCi_CLK high 9.2 ns SDR257 tw(clkL) Pulse duration, MMCi_CLK low 9.2 ns SDR258 td(clkH-cmdV) Delay time, MMCi_CLK rising clock edge to MMCi_CMD transition 2.32 13.18 ns SDR259 td(clkH-dV) Delay time, MMCi_CLK rising clock edge to MMCi_DAT[j:0] transition 2.32 13.18 ns A. There are two MMCi modules: MMC0 and MMC1 MMC[ ]_CLK x MMC[ ]_CMD x MMC DAT [ ]_ [3:0] x SDR251 SDR252 SDR253 SDR254 Figure 7-78. eMMC/SD/SDIO in - SDR25, 1.8-V High-Speed SDR - Receiver Mode www.ti.com AM6548, AM6528, AM6526 SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 217 Product Folder Links: AM6548 AM6528 AM6526 |
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