TC35680FSG datasheet(7/91 Pages) TOSHIBA

7 / 91 page

TC35680FSG-002/TC35681FSG-002

2019-04-04

1.2. Features

 Wireless communication function



Compliant with Bluetooth® Low Energy Ver.5.0 specification.



Built-in Bluetooth® baseband circuit



Built-in Bluetooth® RF circuit



Maximum output power: +8 dBm



Maximum RX sensitivity: -105.0 dBm (in case of Coded PHY and S = 8)



RSSI accuracy: ±2 dB (in case of -90 to -10 dBm input)



HCI commands/Extended HCI commands (implemented in the mask ROM)



Control API in GATT/SM layer (TCU commands: Toshiba Command Unit) (implemented in the mask ROM)



Auto-advertising feature



Output power setting feature

 Microcontroller unit



Built-in Arm® Cortex®-M0 processor (Maximum operating frequency is 32 MHz.)



Built-in mask ROM



Boot loader



API for the hardware control



Bluetooth® wireless function API



Bluetooth® protocol stack



Built-in retention SRAM (User area is 76 KB out of total 144 KB.)



Built-in serial Flash memory (TC35680 only)



Memory capacity: 128 KB



Sector size: 4 KB



Endurance: 100,000 times



Interface, AD converter, and Debug function



General-purpose I/O (GPIO) (18 pins)



General-purpose serial interfaces



UART interface (2 channels. Shared with the GPIO pins.)



HCI mode: One channel is used as a host interface (9600 bps to 921.6 kbps)



User-App mode: 600 to 2000 kbps (Maximum baudrate may be 2000 kbps or less and depends on user-

application program.)



SPI interface (2 channels. Shared with the GPIO pins.)



I2C interface (2 channels. Shared with the GPIO pins.)



TC35681 uses one channel as the interface to the EEPROM for User-App mode.



PWM interface (4 channels. Shared with the GPIO pins.)



Pulse generation function



“Rhythm function” (function to mask a pulse signal)



AD converter (ADC)



General-purpose voltage measurement (5 channels. Shared with the GPIO pins.)



Power supply voltage (VBAT) measurement (1 channel. Connected internally.)



Interface for Emulator debug control



SWD (Serial Wire Debug): 2-wire system (1 channel)



Clock



Reference clock (32 MHz)



Built-in crystal oscillator with a frequency adjustment function



Sleep clock (32.768 kHz)



Built-in crystal oscillator with a frequency adjustment function



External clock input is supported.



Built-in silicon oscillator (SiOSC)



Sleep clock output function (Shared with the GPIO pins.)

TC35680FSG Datasheet(PDF) 7 Page - Toshiba Semiconductor

TC35680FSG Datasheet(HTML) 7 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

Datasheet Download

Link URL