WM8987LGECOSLASHV datasheet(44/58 Pages) WOLFSON

44 / 58 page

WM8987L

Pre-Production

PP Rev 3.0 January 2007

POWER MANAGEMENT

The WM8987L has two control registers that allow users to select which functions are active. For

minimum power consumption, unused functions should be disabled. To avoid any pop or click noise,

it is important to enable or disable functions in the correct order (see Applications Information).

VMIDSEL is the enable for the VMID reference, which defaults to disabled and can be enabled as a

50k

Ω potential divider or, for low power maintenance of VREF when all other blocks are disabled, as

a 500k

Ω potential divider.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

8:7

VMIDSEL

Vmid divider enable and select

00 – Vmid disabled (for OFF mode)

01 – 50k

Ω divider enabled (for

playback/record)

10 – 500k

Ω divider enabled (for low-power

standby)

11 – 5k

Ω divider enabled (for fast start-up)

VREF

VREF (necessary for all other functions)

AINL

Analogue in PGA Left

AINR

Analogue in PGA Right

ADCL

ADC Left

ADCR

ADC Right

R25 (19h)

Power

Management

(1)

MICB

MICBIAS

DACL

DAC Left

DACR

DAC Right

ROUT1

ROUT1 Output Buffer

LOUT2

LOUT2 Output Buffer

ROUT2

ROUT2 Output Buffer

MONO

Mono Mixer

R26 (1Ah)

Power

Management

(2)

OUT3

OUT3 Output Buffer

Notes:

1. All bits except VMIDSEL are 1=on, 0=off.

2. The left mixer is enabled when LOUT2=1.

3. The right mixer is enabled when ROUT1=1 or ROUT2=1.

4. The mono mixer is enabled when MONO=1.

Table 41 Power Management

STOPPING THE MASTER CLOCK

In order to minimise power consumed in the digital core of the WM8987L, the master clock may be

stopped in Standby and OFF modes. If this cannot be done externally at the clock source, the

DIGENB bit (R25, bit 0) can be set to stop the MCLK signal from propagating into the device core. In

Standby mode, setting DIGENB will typically provide an additional power saving on DCVDD of 20uA.

However, since setting DIGENB has no effect on the power consumption of other system

components external to the WM8987L, it is preferable to disable the master clock at its source

wherever possible.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R25 (19h)

Additional Control

(1)

DIGENB

Master clock disable

0: master clock enabled

1: master clock disabled

Table 42 ADC and DAC Oversampling Rate Selection

NOTE: Before DIGENB can be set, the control bits ADCL, ADCR, DACL and DACR must be set

to zero and a waiting time of 1ms must be observed. Any failure to follow this procedure may

prevent DACs and ADCs from re-starting correctly.

WM8987LGECO/V Datasheet(PDF) 44 Page - Wolfson Microelectronics plc

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