SW

FB

B3

R1

G1

B1

G2

SCK/

SCL

IF_

SEL

B2

VDDA

VREF

GND

IRT

VDD1

GND_

RGB2

SS/

SDA

VDD2

SI/A0

R4

ASE1

G4

GNDA

GND_

RGB1

R2

IRGB

SO

VDDI

O

ASE2

G3

ALED

NRST

GND_

SW

R3

B4

GND

Route sensitive FB node away

from high dv/dt nodes and keep

as short as possible.

Short wide paths on all high di/dt nodes

(SW, GND_SW, VOUT).

Keep current loops as short as possible.

COUT

L1

CIN

TOP Layer GND plane connecting

SW_GND to COUT and CIN.

Connect to system ground using as

many vias as possible.

GND

VOUT

VDD

Copyright © 2016, Texas Instruments Incorporated

36

LP55281

SNVS458D – JUNE 2007 – REVISED OCTOBER 2016

www.ti.com

Product Folder Links: LP55281

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Copyright © 2007–2016, Texas Instruments Incorporated

Layout Guidelines (continued)

10.1.4 Boost Input Capacitor Placement

Close placement of the input capacitor to the IN pin and to the GND pin is critical because any series inductance

between IN and CIN+ or CIN

− and GND can create voltage spikes that could appear on the VIN supply line and

in the GND plane. Close placement of the input bypass capacitor at the input side of the inductor is also critical.

10.2 Layout Example

Figure 32. LP55281 Layout