ADF4206/ADF4208

Rev. A | Page 5 of 24

TIMING SPECIFICATIONS

VDD1 = VDD2 = 3 V ± 10%, 5 V ± 10%; VDD1, VDD2 ≤ VP1, VP2 ≤ 6.0 V; AGNDRF1 = DGNDRF1 = AGNDRF2 = DGNDRF2 = 0 V;

TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 Ω.

Table 2.

Parameter1

Limit at TMIN to TMAX (B Version)

Unit

Test Conditions/Comments

t1

10

ns min

DATA to CLK setup time

t2

10

ns min

DATA to CLK hold time

t3

25

ns min

CLK high duration

t4

25

ns min

CLK low duration

t5

10

ns min

CLK to LE setup time

t6

20

ns min

LE pulse width

1 Guaranteed by design but not production tested.

TIMING DIAGRAM

DB0 (LSB)

(CONTROL BIT C1)

CLK

DB21 (MSB)

DB20

DB2

DATA

LE

LE

t3

t4

t2

t5

t1

t6

DB1

(CONTROL BIT C2)

Figure 2. Timing Diagram