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H8SX1663 Datasheet(PDF) 425 Page - Renesas Technology Corp |
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H8SX1663 Datasheet(HTML) 425 Page - Renesas Technology Corp |
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425 / 1158 page  Section 7 DMA Controller (DMAC) Rev.1.00 Jun. 07, 2006 Page 373 of 1102 REJ09B0294-0100 (2) Normal Transfer Mode (Burst Mode) In burst mode, one byte, one word, or one longword of data continues to be transferred until the transfer end condition is satisfied. When a burst transfer starts, a transfer request from a channel having priority is suspended until the burst transfer is completed. In figure 7.27, the TEND signal output is enabled and data is transferred in words from the external 16-bit 2-state access space to the external 16-bit 2-state access space in normal transfer mode by burst access. DMA read cycle DMA read cycle DMA write cycle Address bus DMA write cycle DMA read cycle DMA write cycle B φ RD LHWR, LLWR TEND Bus released Bus released Last transfer cycle Burst transfer Figure 7.27 Example of Transfer in Normal Transfer Mode by Burst Access |
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