STM32F102C4 datasheet(46/69 Pages) STMICROELECTRONICS

46 / 69 page

Electrical characteristics

STM32F102x4, STM32F102x6

46/69

Doc ID 15057 Rev 3

5.3.11

Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is

stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size

depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test

conforms to the JESD22-A114/C101 standard.

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up

performance:

●

A supply overvoltage is applied to each power supply pin

●

A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78 IC latch-up standard.

Table 30.

EMI characteristics

Symbol Parameter

Conditions

Monitored

frequency band

Max vs. [fHSE/fHCLK]

Unit

8/48 MHz

SEMI

Peak level

VDD 3.3 V, TA 25 °C,

0.1 MHz to 30 MHz

dBµV

30 MHz to 130 MHz

130 MHz to 1GHz

SAE EMI Level

3.5

Table 31.

ESD absolute maximum ratings

Symbol

Ratings

Conditions

Class

Maximum

value(1)

Based on characterization results, not tested in production.

Unit

VESD(HBM)

Electrostatic discharge voltage

(human body model)

TA +25 °C, conforming

to JESD22-A114

2000

VESD(CDM)

Electrostatic discharge voltage

(charge device model)

TA +25 °C, conforming

to JESD22-C101

500

Table 32.

Electrical sensitivities

Symbol

Parameter

Conditions

Class

Static latch-up class

TA +105 °C conforming to JESD78A

II level A

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