HT45B0F datasheet(15/23 Pages) HOLTEK

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HT45B0F

Rev. 1.00

June 7, 2011

· UART transmitter

Data word lengths of either 8 or 9 bits can be selected

by programming the BNO bit in the UCR1 register.

When BNO bit is set, the word length will be set to 9

bits. In this case the 9th bit, which is the MSB, needs

to be stored in the TX8 bit in the UCR1 register. At the

transmitter core lies the Transmitter Shift Register,

more commonly known as the TSR, whose data is ob-

tained from the transmit data register, which is known

as the TXR register. The data to be transmitted is

loaded into this TXR register by the application pro-

gram. The TSR register is not written to with new data

until the stop bit from the previous transmission has

been sent out. As soon as this stop bit has been trans-

mitted, the TSR can then be loaded with new data

from the TXR register, if it is available. It should be

noted that the TSR register, unlike many other regis-

ters, is not directly mapped into the Data Memory area

and as such is not available to the application program

for direct read/write operations. An actual transmis-

sion of data will normally be enabled when the TXEN

bit is set, but the data will not be transmitted until the

TXR register has been loaded with data and the baud

rate generator has defined a shift clock source. How-

ever, the transmission can also be initiated by first

loading data into the TXR register, after which the

TXEN bit can be set. When a transmission of data be-

gins, the TSR is normally empty, in which case a

transfer to the TXR register will result in an immediate

transfer to the TSR. If during a transmission the TXEN

bit is cleared, the transmission will immediately cease

and the transmitter will be reset. The TX output pin will

then return to the high impedance state.

· Transmitting data

When the UART is transmitting data, the data is

shifted on the TX pin from the shift register, with the

least significant bit LSB first. In the transmit mode, the

TXR register forms a buffer between the internal bus

and the transmitter shift register. It should be noted

that if 9-bit data format has been selected, then the

MSB will be taken from the TX8 bit in the UCR1 regis-

ter. The steps to initiate a data transfer can be sum-

marized as follows:

¨ Make the correct selection of the BNO, PRT, PREN

and STOPS bits to define the required word length,

parity type and number of stop bits.

¨ Setup the BRG register to select the desired baud

rate.

¨ Set the TXEN bit to ensure that the UART transmit-

ter is enabled and the TX pin is used as a UART

transmitter pin.

¨ Access the USR register and write the data that is to

be transmitted into the TXR register. Note that this

step will clear the TXIF bit.

This sequence of events can now be repeated to send

additional data.

It should be noted that when TXIF=0, data will be in-

hibited from being written to the TXR register. Clearing

the TXIF flag is always achieved using the following

software sequence:

1. A USR register access

2. A TXR register write execution

The read-only TXIF flag is set by the UART hardware

and if set indicates that the TXR register is empty and

that other data can now be written into the TXR regis-

ter without overwriting the previous data. If the TEIE

bit is set, then the TXIF flag will generate an interrupt.

During a data transmission, a write instruction to the

TXR register will place the data into the TXR register,

which will be copied to the shift register at the end of

the present transmission. When there is no data trans-

mission in progress, a write instruction to the TXR reg-

ister will place the data directly into the shift register,

resulting in the commencement of data transmission,

and the TXIF bit being immediately set. When a frame

transmission is complete, which happens after stop

bits are sent or after the break frame, the TIDLE bit will

be set. To clear the TIDLE bit the following software

sequence is used:

1. A USR register access

2. A TXR register write execution

Note that both the TXIF and TIDLE bits are cleared by

the same software sequence.

· Transmitting break

If the TXBRK bit is set, then the break characters will

be sent on the next transmission. Break character

transmission consists of a start bit, followed by 13

´N

²0² bits, where N=1, 2, etc. if a break character is to be

transmitted, then the TXBRK bit must be first set by

the application program and then cleared to generate

the stop bits. Transmitting a break character will not

generate a transmit interrupt. Note that a break condi-

tion length is at least 13 bits long. If the TXBRK bit is

continually kept at a logic high level, then the transmit-

ter circuitry will transmit continuous break characters.

After the application program has cleared the TXBRK

bit, the transmitter will finish transmitting the last break

character and subsequently send out one or two stop

bits. The automatic logic high at the end of the last

break character will ensure that the start bit of the next

frame is recognized.

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