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CPLL Datasheet(PDF) 12 Page - Exar Corporation |
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CPLL Datasheet(HTML) 12 Page - Exar Corporation |
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12 / 29 page  X XR RP P7 77 72 24 4 Q Qu ua ad d C Ch ha an nn ne ell D Diig giitta all P PW WM M/ /P PF FM M P Prro og grra am mm ma ab blle e P Po ow we err M Ma an na ag ge em me en ntt S Sy ys stte em m © 2012 Exar Corporation 12/29 Rev. 1.0.1 FEATURES AND BENEFITS Programmable Power Benefits Fully Configurable Output set point Feedback compensation Frequency set point Under voltage lock out Input voltage measurement Gate drive dead time Reduced Development Time Configurable and re-configurable for different Vout, Iout, Cout, and Inductor values No need to change external passives for a new output specification. Higher integration and Reliability Many external circuits used in the past can be eliminated significantly improving reliability. PowerArchitect™ 5.0 Design and Configuration Software Wizard quickly generates a base design Calculates all configuration registers Projects can be saved and/or recalled GPIOs can be configured easily and intuitively “Dashboard” Interface can be used for real-time monitoring and debug System Benefits Reliability is enhanced via communication with the system controller which can obtain real time data on an output voltage, input voltage and current. System processors can communicate with the XRP7724 directly to obtain data or make adjustments to react to circuit conditions A system process or could also be configured to log and analyze operating history, perform diagnostics and if required, take the supply off-line after making other system adjustments. System Integration Capabilities Single supply operation I2C interface allows: Communication with a System Controller or other Power Management devices for optimized system function Access to modify or read internal registers that control or monitor: Output Current Input and Output Voltage Soft-Start/Soft-Stop Time ‘Power Good’ Part Temperature Enable/Disable Outputs Over Current Over Voltage Temperature Faults Adjusting fault limits and disabling/enabling faults Packet Error Checking (PEC) on I2C communication 5 GPIO pins with a wide range of configurability Fault reporting (including UVLO Warn/Fault, OCP Warn/Fault, OVP, Temperature, Soft-Start in progress, Power Good, System Reset) Allows a Logic Level interface with other non-digital IC’s or as logic inputs to other devices Frequency and Synchronization Capability Selectable switching frequency between 105kHz and 1.2MHz Main oscillator clock and DPWM clock can be synchronized to external sources ‘Master’, ‘Slave’ and ‘Stand-alone’ Configurations are possible Internal MOSFET Drivers Internal FET drivers (4Ω/2Ω) per channel Built-In Automatic Dead-time adjustment 30ns Rise and Fall times 4 Independent SMPS channels and 2 LDOs in a 7x7mm TQFN |
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