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CPLL Datasheet(PDF) 6 Page - Exar Corporation

Part # CPLL
Description  Quad Channel Digital PWM/PFM Programmable Power Management System
PDF  29 Pages
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Manufacturer  EXAR [Exar Corporation]
Direct Link  http://www.exar.com
Logo EXAR - Exar Corporation

CPLL Datasheet(HTML) 6 Page - Exar Corporation

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© 2012 Exar Corporation
6/29
Rev. 1.0.1
SMBUS (I2C) INTERFACE
Parameter
Min.
Typ.
Max.
Units
Conditions
Input Pin Low Level, VIL
0.3 VIO
V
VIO = 3.3 V ±10%
Input Pin High Level, VIH
0.7 VIO
V
VIO = 3.3 V±10%
Hysteresis of Schmitt Trigger
inputs, Vhys
0.05 VIO
V
VIO = 3.3 V±10%
Output Pin Low Level (open
drain or collector), VOL
0.4
V
ISINK = 3mA
Input leakage current
-10
10
µA
Input is between 0.1 VIO and 0.9 VIO
Output fall time from VIHmin to
VILmax
20 + 0.1
Cb
250
ns
With a bus capacitance (Cb)from 10 pF to
400 pF
Internal Pin Capacitance
1
pF
GATE DRIVERS
Parameter
Min.
Typ.
Max.
Units
Conditions
GH, GL Rise Time
17
ns
At 10-90% of full scale, 1nF Cload
GH, GL Fall Time
11
ns
GH, GL Pull-Up On-State Output
Resistance
4
5
Ω
GH, GL Pull-Down On-State
Output Resistance
2
2.5
Ω
GH, GL Pull-Down Resistance in
Off-Mode
50
kΩ
VCC = VCCD = 0V.
Bootstrap diode forward
resistance
9
Ω
@ 10mA
Minimum On Time
50
ns
1nF of gate capacitance.
Minimum Off Time
125
ns
1nF of gate capacitance
Minimum Programmable Dead
Time
20
ns
Does not include dead time variation from
driver output stage
Tsw=switching period
Maximum Programmable Dead
Time
Tsw
Programmable Dead Time
Adjustment Step
607
ps



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