LCMXO2-640ZE-1TG100C datasheet(37/106 Pages) LATTICE

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Architecture

MachXO2 Family Data Sheet

Table 2-18. MachXO2 Power Saving Features Description

For more details on the standby mode refer to TN1198, Power Estimation and Management for MachXO2 Devices.

Power On Reset

MachXO2 devices have power-on reset circuitry to monitor VCCINT and VCCIO voltage levels during power-up and

operation. At power-up, the POR circuitry monitors VCCINT and VCCIO0 (controls configuration) voltage levels. It

then triggers download from the on-chip configuration Flash memory after reaching the VPORUP level specified in

the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet. For devices

without voltage regulators (ZE and HE devices), VCCINT is the same as the VCC supply voltage. For devices with

voltage regulators (HC devices), VCCINT is regulated from the VCC supply voltage. From this voltage reference, the

time taken for configuration and entry into user mode is specified as Flash Download Time (tREFRESH) in the DC

and Switching Characteristics section of this data sheet. Before and during configuration, the I/Os are held in tri-

state. I/Os are released to user functionality once the device has finished configuration. Note that for HC devices, a

separate POR circuit monitors external VCC voltage in addition to the POR circuit that monitors the internal post-

regulated power supply voltage level.

Once the device enters into user mode, the POR circuitry can optionally continue to monitor VCCINT levels. If

VCCINT drops below VPORDNBG level (with the bandgap circuitry switched on) or below VPORDNSRAM level (with the

bandgap circuitry switched off to conserve power) device functionality cannot be guaranteed. In such a situation

the POR issues a reset and begins monitoring the VCCINT and VCCIO voltage levels. VPORDNBG and VPORDNSRAM

are both specified in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data

sheet.

Note that once a ZE or HE device enters user mode, users can switch off the bandgap to conserve power. When

the bandgap circuitry is switched off, the POR circuitry also shuts down. The device is designed such that a mini-

mal, low power POR circuit is still operational (this corresponds to the VPORDNSRAM reset point described in the

paragraph above). However this circuit is not as accurate as the one that operates when the bandgap is switched

on. The low power POR circuit emulates an SRAM cell and is biased to trip before the vast majority of SRAM cells

flip. If users are concerned about the VCC supply dropping below VCC (min) they should not shut down the bandgap

or POR circuit.

Device Subsystem

Feature Description

Bandgap

The bandgap can be turned off in standby mode. When the Bandgap is turned off, ana-

log circuitry such as the POR, PLLs, on-chip oscillator, and referenced and differential



I/O buffers are also turned off. Bandgap can only be turned off for 1.2V devices.

Power-On-Reset (POR)

The POR can be turned off in standby mode. This monitors VCC levels. In the event of

unsafe VCC drops, this circuit reconfigures the device. When the POR circuitry is turned

off, limited power detector circuitry is still active. This option is only recommended for ap-

plications in which the power supply rails are reliable.

On-Chip Oscillator

The on-chip oscillator has two power saving features. It may be switched off if it is not

needed in your design. It can also be turned off in Standby mode.

PLL

Similar to the on-chip oscillator, the PLL also has two power saving features. It can be

statically switched off if it is not needed in a design. It can also be turned off in Standby

mode. The PLL will wait until all output clocks from the PLL are driven low before power-

ing off.

I/O Bank Controller

Referenced and differential I/O buffers (used to implement standards such as HSTL,

SSTL and LVDS) consume more than ratioed single-ended I/Os such as LVCMOS and

LVTTL. The I/O bank controller allows the user to turn these I/Os off dynamically on a

per bank selection.

Dynamic Clock Enable for Primary

Clock Nets

Each primary clock net can be dynamically disabled to save power.

Power Guard

Power Guard is a feature implemented in input buffers. This feature allows users to

switch off the input buffer when it is not needed. This feature can be used in both clock

and data paths. Its biggest impact is that in the standby mode it can be used to switch off

clock inputs that are distributed using general routing resources.

LCMXO2-640ZE-1TG100C Datasheet(PDF) 37 Page - Lattice Semiconductor

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