LCMXO2-640ZE-1TG100C datasheet(47/106 Pages) LATTICE

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3-8

DC and Switching Characteristics

MachXO2 Family Data Sheet

sysIO Single-Ended DC Electrical Characteristics

1, 2

Input/Output

Standard

VIL

VIH

VOL Max.

(V)

VOH Min.

(V)

IOL Max.

(mA)

IOH Max.

(mA)

Min. (V)

Max. (V)

Min. (V)

Max. (V)

LVCMOS 3.3

LVTTL

-0.3

0.8

2.0

3.6

0.4

VCCIO - 0.4

4-4

8-8

-12

-16

-24

0.2

VCCIO - 0.2

0.1

-0.1

LVCMOS 2.5

-0.3

0.7

1.7

3.6

0.4

VCCIO - 0.4

4-4

8-8

-12

-16

0.2

VCCIO - 0.2

0.1

-0.1

LVCMOS 1.8

-0.3

0.35VCCIO

0.65VCCIO

3.6

0.4

VCCIO - 0.4

4-4

8-8

-12

0.2

VCCIO - 0.2

0.1

-0.1

LVCMOS 1.5

-0.3

0.35VCCIO

0.65VCCIO

3.6

0.4

VCCIO - 0.4

4-4

8-8

0.2

VCCIO - 0.2

0.1

-0.1

LVCMOS 1.2

-0.3

0.35VCCIO

0.65VCCIO

3.6

0.4

VCCIO - 0.4

4-2

8-6

0.2

VCCIO - 0.2

0.1

-0.1

PCI

-0.3

0.3VCCIO

0.5VCCIO

3.6

0.1VCCIO

0.9VCCIO

1.5

-0.5

SSTL25 Class I

-0.3

VREF - 0.18 VREF + 0.18

3.6

0.54

VCCIO - 0.62

SSTL25 Class II

-0.3

VREF - 0.18

VREF +0.18

3.6

SSTL18 Class I

-0.3

VREF - 0.125 VREF +0.125

3.6

0.40

VCCIO - 0.40

SSTL18 Class II

-0.3

VREF - 0.125 VREF +0.125

3.6

HSTL18 Class I

-0.3

VREF - 0.1

VREF +0.1

3.6

0.40

VCCIO - 0.40

HSTL18 Class II

-0.3

VREF - 0.1

VREF +0.1

3.6

1. MachXO2 devices allow LVCMOS inputs to be placed in I/O banks where VCCIO is different from what is specified in the applicable JEDEC

specification. This is referred to as a ratioed input buffer. In a majority of cases this operation follows or exceeds the applicable JEDEC spec-

ification. The cases where MachXO2 devices do not meet the relevant JEDEC specification are documented in the table below.

2. MachXO2 devices allow for LVCMOS referenced I/Os which follow applicable JEDEC specifications. For more details about mixed mode

operation please refer to please refer to TN1202, MachXO2 sysIO Usage Guide.

3. The dual function I

2C pins SCL and SDA are limited to a VIL min of -0.25V or to -0.3V with a duration of <10ns.

4. The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O bank and the end of an I/O bank, as

shown in the logic signal connections table shall not exceed n * 8mA. Where n is the number of I/Os between bank GND connections or

between the last GND in a bank and the end of a bank.

Input Standard

VCCIO (V)

VIL Max. (V)

LVCMOS 33

1.5

0.685

LVCMOS 25

1.5

1.687

LVCMOS 18

1.5

1.164

LCMXO2-640ZE-1TG100C Datasheet(PDF) 47 Page - Lattice Semiconductor

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