LCMXO2-640ZE-1TG100C datasheet(16/106 Pages) LATTICE

16 / 106 page

2-12

Architecture

MachXO2 Family Data Sheet

The EBR memory supports three forms of write behavior for single or dual port operation:

Normal – Data on the output appears only during the read cycle. During a write cycle, the data (at the current

address) does not appear on the output. This mode is supported for all data widths.

Write Through – A copy of the input data appears at the output of the same port. This mode is supported for

all data widths.

Read-Before-Write – When new data is being written, the old contents of the address appears at the output.

FIFO Configuration

The FIFO has a write port with data-in, CEW, WE and CLKW signals. There is a separate read port with data-out,

RCE, RE and CLKR signals. The FIFO internally generates Almost Full, Full, Almost Empty and Empty Flags. The

Full and Almost Full flags are registered with CLKW. The Empty and Almost Empty flags are registered with CLKR.

Table 2-7 shows the range of programming values for these flags.

Table 2-7. Programmable FIFO Flag Ranges

The FIFO state machine supports two types of reset signals: RST and RPRST. The RST signal is a global reset

that clears the contents of the FIFO by resetting the read/write pointer and puts the FIFO flags in their initial reset

state. The RPRST signal is used to reset the read pointer. The purpose of this reset is to retransmit the data that is

in the FIFO. In these applications it is important to keep careful track of when a packet is written into or read from

the FIFO.

Memory Core Reset

The memory core contains data output latches for ports A and B. These are simple latches that can be reset syn-

chronously or asynchronously. RSTA and RSTB are local signals, which reset the output latches associated with

port A and port B respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and

associated resets for both ports are as shown in Figure 2-9.

Figure 2-9. Memory Core Reset

Flag Name

Programming Range

Full (FF)

1 to max (up to 2

N-1)

Almost Full (AF)

1 to Full-1

Almost Empty (AE)

1 to Full-1

Empty (EF)

N = Address bit width.

SET

Output Data

Latches

Memory Core

Port A[18:0]

SET

Port B[18:0]

RSTB

GSRN

Programmable Disable

RSTA

LCMXO2-640ZE-1TG100C Datasheet(PDF) 16 Page - Lattice Semiconductor

LCMXO2-640ZE-1TG100C Datasheet(HTML) 16 Page - Lattice Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL