ISP1507CBS datasheet(7/74 Pages) NXP

7 / 74 page

ISP1507C_ISP1507D_1

Product data sheet

Rev. 01 — 28 May 2008

7 of 74

NXP Semiconductors

ISP1507C; ISP1507D

ULPI HS USB host and peripheral transceiver

Functional description

7.1 ULPI controller

The ISP1507 provides a 12-pin interface that is compliant with

UTMI+ Low Pin Interface

(ULPI) Speciﬁcation Rev. 1.1. This interface must be connected to the USB link.

The ULPI controller provides the following functions:

• ULPI compliant and register set

• Allows full control over the USB peripheral, host and SRP functionality

• Parses the USB transmit and receive data

• Prioritizes the USB receive data, USB transmit data, interrupts and register operations

• Low-power mode

• External VBUS source control

• VBUS monitoring, charging and discharging

• 6-pin serial mode and 3-pin serial mode

• Generates RXCMDs; status updates

• Maskable interrupts

For more information on the ULPI protocol, see Section 9.

7.2 USB serializer and deserializer

The USB data serializer prepares data to transmit on the USB bus. To transmit data, the

USB link sends a transmit command and data on the ULPI bus. The serializer performs

parallel-to-serial conversion, bit stufﬁng and NRZI encoding. For packets with a PID, the

serializer adds a SYNC pattern to the start of the packet, and an EOP pattern to the end

of the packet. When the serializer is busy and cannot accept any more data, the ULPI

controller deasserts NXT.

The USB data deserializer decodes data received from the USB bus. When data is

received, the deserializer strips the SYNC and EOP patterns, and then performs

serial-to-parallel conversion, NRZI decoding and discarding of stuff bits on the data

payload. The ULPI controller sends data to the USB link by asserting DIR, and then

asserting NXT whenever a byte is ready. The deserializer also detects various receive

errors, including bit stuff errors, elasticity buffer underrun or overrun, and byte-alignment

errors.

7.3 Hi-Speed USB (USB 2.0) ATX

The Hi-Speed USB ATX block is an analog front-end containing the circuitry needed to

transmit, receive and terminate the USB bus in high-speed, full-speed and low-speed, for

USB peripheral, host and OTG implementations. The following circuitry is included:

• Differential drivers to transmit data at high-speed, full-speed and low-speed

• Differential and single-ended receivers to receive data at high-speed, full-speed and

low-speed

• Squelch circuit to detect high-speed bus activity

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