80960KB datasheet(23/44 Pages) INTEL

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80960KB

2.8.1

AC Specification Tables

1. Clock rise and fall times are not tested.

2. A float condition occurs when the maximum output current becomes less than ILO. Float delay is not tested; however, it

should not be longer than the valid delay.

3. LAD31:0, BADAC, HOLD, LOCK and READY are synchronous inputs. IAC/INT0, INT1, INT2/INTR and INT3 may be syn-

chronous or asynchronous.

Table 7. 80960KB AC Characteristics (16 MHz)

Symbol

Parameter

Min

Max

Units

Notes

Input Clock

Processor Clock Period (CLK2)

31.25

125

VIN = 1.5V

Processor Clock Low Time (CLK2)

VIL = 10% Point = 1.2V

Processor Clock High Time (CLK2)

VIH = 90% Point = 0.1V + 0.5 VCC

Processor Clock Fall Time (CLK2)

VIN = 90% Point to 10% Point (1)

Processor Clock Rise Time (CLK2)

VIN = 10% Point to 90% Point (1)

Synchronous Outputs

Output Valid Delay

T6H

HLDA Output Valid Delay

ALE Width

ALE Output Valid Delay

Output Float Delay

(2)

T9H

HLDA Output Float Delay

(2)

Synchronous Inputs

T10

Input Setup 1

(3)

T11

Input Hold

(3)

T11H

HOLD Input Hold

(3)

T12

Input Setup 2

(3)

T13

Setup to ALE Inactive

T14

Hold after ALE Inactive

T15

Reset Hold

(3)

T16

Reset Setup

(3)

T17

Reset Width

1281

41 CLK2 Periods Minimum

NOTES:

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