AN3317

Low-inductance capacitor layout in high-frequency applications

Doc ID 18249 Rev 2

19/22

Appendix A

Low-inductance capacitor layout in

high-frequency applications

Figure 5 shows several decoupling capacitor layouts.

Do not use layouts a or b. These layouts have inherently high inductance, and thus a high

impedance at high frequencies.

Use layout d or e for high frequency decoupling applications. These layouts have low

inductance.

●

Where space allows, use the 4-via layout (e), which has the lowest inductance but

requires more board area.

●

Where space does not permit the 4-via layout, the 2-via layout (d) is a good

compromise.

Use layout c as a last resort when there is no space for either layout d or e.

Figure 5.

Decoupling capacitor layouts

A.1

0402 package compact land pattern

An area-efficient compact land pattern facilitates PCB layout of decoupling capacitors.

Figure 6 shows a commonly used land pattern.

Figure 6.

0402 package compact land pattern

Table 4.

0402 package compact land pattern dimensions

Dimension

Distance (mil)

A20

B20

C15