SC14CVMDECT-SF datasheet(31/57 Pages) DIALOG

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Datasheet

Revision 3.0

28-Jul-2015

CFR0011-120-00-FM Rev 5

31 of 57

SC14CVMDECT SF

Cordless Voice Module

FINAL

Note 12: P1[5] is output from reset to supply an external EEPROM.

P1[6] and P1[]7 are pull-down only., P3[0], P3[1] are output only

P2[0], P2[1] pull-up resistors are disabled in PAD_CTRL_REG[P20_OD, P21_OD] = 1.

If P3[3] and P1[0] are set to output, the ADC0 and ADC1 inputs are automatically disabled.

R0/W

Px_3_RESET

If Px[3] output, writing a 1 resets Px[3] to 0. Writing 0 is discarded.

Reading returns 0

R0/W

Px_2_RESET

If Px[2] output, writing a 1 resets Px[2] to 0. Writing 0 is discarded.

Reading returns 0

R0/W

Px_1_RESET

If Px[1] output, writing a 1 resets Px[1] to 0. Writing 0 is discarded.

Reading returns 0

R0/W

Px_0_RESET

If Px[0] output, writing a 1 resets Px[0] to 0. Writing 0 is discarded.

Reading returns 0

NOTE:

x = 0, 1, 2, 3 These registers are not reset with a SW reset

Table 11: P0_DIR_REG, P1_DIR_REG, P2_DIR_REG, P3_DIR_REG (0xFF4836, 0xFF4846, 0xFF4856,

0xFF4866)

Bit

Mode

Symbol

Description

Reset

P0-P5

15-14

R/W

Px_7_DIR

00 = Input, no resistors selected

01 = Input, pull-up selected

10 = Input, Pull-down selected

11 = Output, no resistors selected

In analog mode, these bits must be set to 0 to disable resistors

and digital output mode.

1,-,1,0

13-12

R/W

Px_6_DIR

1,-,1,0

11-10

R/W

Px_5_DIR

1,3,1,0

9-8

R/W

Px_4_DIR

1,2,1,0

7-6

R/W

Px_3_DIR

1,2,1,0

5-4

R/W

Px_2_DIR

1,1,1,0

3-2

R/W

Px_1_DIR

1,1,1,-

1-0

R/W

Px_0_DIR

1,1,1,-

NOTE:x = 0,1,2,3,4,5 These registers are not reset with a SW reset

Table 12: P0_MODE_REG (0xFF4838)

Bit

Mode

Symbol

Description

Reset

15-14

13-12

R/W

P0_7_MODE

00 = P0_OUT_DATA_REG[7] on P0[7]

01 = SPI_DI on P0[7] (don’t care)

10 = Timer 0 PWM1 on P0[7]

11 = Reserved

11-10

R/W

P0_6_MODE

00 = P0_OUT_DATA_REG[6] on P0[6]

01 = SPI_DO on P0[6]

10 = Reserved

11 = Reserved

9-8

R/W

P0_5_MODE

00 = P0_OUT_DATA_REG[5] on P0[5]

01 = SPI_CLK on P0[5]

10 = Reserved

11 = Reserved

7-6

R/W

P0_4_MODE

00 = P0_OUT_DATA_REG[4] on P0[4]

01 = SPI_EN input on P0[4] (don’t care)

10 = Reserved

11 = Reserved

Table 10: P0_RESET_DATA_REG, P1_RESET_DATA_REG, P2_RESET_DATA_REG, P3_RESET_DATA_REG

(0xFF4834, 0xFF4844, 0xFF4854, 0xFF4864)

Bit

Mode

Symbol

Description

Reset

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