AX88780 datasheet(10/49 Pages) ASIX

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AX88780

2.4 Regulator Interface

Table 3 : Regulator signals group

Pin Name Type

Pin No.

Pin Description

VCC33R

VCC3R

3.3V power to internal regulator

GNDR

Ground pin for internal regulator

REG_EN

High to enable internal regulator. Low to disable internal regulator.

V25OUT

2.5V output from internal regulator, max 250mA, when REG_EN pin is high.

2.5 10/100M PHY Interface

Table 4 : 10/100M Twisted-pair signals group

Pin Name

Type

Pin No.

Pin Description

RXIN

Differential received input signal for both 10BASE-T and 100BSE-TX modes.

RXIP

Differential received input signal for both 10BASE-T and 100BSE-TX modes.

TXON

Differential transmitted output signal for both 10BASE-T and 100BASE-TX modes.

TXOP

Differential transmitted output signal for both 10BASE-T and 100BASE-TX modes

2.6 MII Interface (optional)

Table 5 : MII Interface signals group

Pin Name

Type

Pin No.

Pin Description

TXEN

O2, 12mA

Transmit Enable:

TXEN is transition synchronously with respect to the rising edge of TXCLK. TXEN

indicates that the port is presenting nibbles on TXD [3:0] for transmission.

TXD[3:0]

O2, 12mA

61,62,

63,65

Transmit Data:

TXD[3:0] is transition synchronously with respect to the rising edge of TXCLK.

TXCLK

Transmit Clock:

TXCLK is a continuous clock from PHY. It provides the timing reference for the

transfer of the TXEN and TXD[3:0] signals from the MII port of PHY.

RXCLK

Receive Clock:

RXCLK is a continuous clock that provides the timing reference for the transfer of the

RXDV, RXD[3:0].

RXD[3:0]

74,75,

76,77

Receive Data:

RXD[3:0] is driven by the PHY synchronously with respect to RXCLK.

RXDV

Receive Data Valid:

RXDV is driven by the PHY synchronously with respect to RXCLK. Asserted high

when valid data is present on RXD [3:0].

COL

Collision signal:

This signal is driven by PHY when collision is detected.

CRS

Carrier Sense:

Asynchronous signal CRS is asserted by the PHY when either the transmit or receive

medium is non-idle.

MDIO

IO3,

8mA,PU

Station Management Data Input /Output:

Serial data input/Output transfers from/to the PHY. The transfer protocol conforms to

the IEEE 802.3u MII specification.

MDC

O3, 8mA

Station Management Data Clock:

The timing reference for MDIO. All data transfers on MDIO are synchronized to the

rising edge of this clock.

PHYINTN I2

An interrupt signal from PHY, active low.

ASIX ELECTRONICS CORPORATION

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