ACT41000-102 datasheet(7/72 Pages) QORVO

7 / 72 page

ACT41000

Programmable Voltage, Programmable Current, Low Noise

RFPoL Step-Down Voltage Regulator

PARAMETER

SYMBOL

TEST CONDITION

MIN

TYP

MAX

UNIT

SYNC Pin Input

Threshold

VIT(SYNC)

SYNC pin in slave

0.55

1.4

VOH(SYNC)

SYNC pin in master, outputs logic-H

3.2

V5V

SYNC Pin Output

Voltage

VOL(SYNC)

SYNC pin in master, outputs logic-L

0.8

C PINS

Input Threshold

VIT(I2C)

SDA and SCL pins

0.55

1.25

Leakage Current

ILK(SDA)

VSDA = 5 V

µA

Output Voltage

VOL(SDA)

5 mA Current into SDA pin

0.35

Input Capacitance

CI(I2C)

SDA and SCL pins

MAIN-BUCK REGULATOR

VDACOUT(24)

24 V target (DACOUT[10:0] = 0x780), 50 µA

current DACOUT sourcing

-0.5%

3.0

+0.5%

VDACOUT(5)

5 V target (DACOUT[10:0] = 0x190), 50 µA

current DACOUT sourcing

-0.5%

0.625

+0.5%

DACOUT Accuracy

ΔV

DACOUT

VDACOUT(n+1) - VDACOUT(n)

1.5625

FB_VO Accuracy

W.r.t. VREFIN, VREFIN = 3 V

-1%

ILIM(100)

100% target (ILIM[7:0] = 0xFF)

98.5

101.5

ILIM(25)

25% target (ILIM[7:0] = 0x3F)

24.25

25.75

Output Current Limit

Programming Accuracy

ΔI

LIM

ILIM(n+1) - ILIM(n)

0.4

µA

VCCMODE(100) Differential voltage (VFB_VO - VCSN) at VLIM =

1.6 V

78.5

81.5

Constant Current

Operation Programming

Accuracy

VCCMODE(25) Differential voltage (VFB_VO - VCSN) at VLIM =

0.4 V

19.3

20.7

PG Output Voltage

VOL(PG)

PG at logic-L, 1 mA Current into PG pin

0.3

PG Threshold Upper

Limit

[1]

VIH(VO)

Threshold of Reg03[2], VO_FB w.r.t. VREFIN,

VREFIN = 3 V

+5%

+8%

PG Threshold Lower

Limit

[1]

VIL(VO)

Threshold of Reg03[2], VO_FB w.r.t. VREFIN,

VREFIN = 3 V

-8%

-5%

FB_VO

Over-voltage

VOVP

VO_FB w.r.t. VREFIN, VREFIN = 3 V

+8%

VUVP(CC)

Reg0B[3] = logic-L, VO_FB w.r.t. VREFIN,

VREFIN = 3 V

2.7

2.76

FB_VO

Under-voltage

[2]

VUVP(CV)

Reg0B[3] = logic-H, VO_FB w.r.t. VREFIN,

VREFIN = 3 V

-8%

VIT(CC,rise)

Enable CC loop, Reg09[3] = logic-H, VO_FB

rising

2.3

2.5

FB_VO

Constant Current

Activation Threshold

VIT(CC,fall)

Disable CC loop, Reg09[3] = logic-H, VO_FB

falling

2.2

IOCP(CBC,high) High-side FET limit to trigger

5.5

Main-buck Cycle-by-

cycle Current Limit

IOCP(CBC,low) Low-side FET limit to release

4.2

ACT41000 Data Sheet, Rev. B, 01-Apr-2022

Subject to change without notice

ACT41000-102 Datasheet(PDF) 7 Page - Qorvo, Inc

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