ACT41000-103 datasheet(45/72 Pages) QORVO

45 / 72 page

ACT41000

Programmable Voltage, Programmable Current, Low Noise

RFPoL Step-Down Voltage Regulator

avoid an inconsistent PG output, the Servo Reference Control blocks the PG pin regardless of voltage or

current target changes.

Main-buck Power-Good Detail

The PG pin indicates the device is in a regulation of either CV or CC. When the PG pin is "good", the device provides

multiple bits for the detail of this power-good operation through the I

2C.

The Reg03[4] bit indicates whether the device in CV or CC.

The Reg03[2] bit indicates whether the device in the CV regulation window of the VIH(VO) and VIL(VO) thresholds.

The Reg01[7] bit indicates a transition between CV or CC.

Main-buck Power-Good Delay

The PG block has a programmable delay circuit at the output stage of the PG pin. The device can insert a certain delay time

from the timing of device internal power-good judgement to actual PG pin transition. This programmable delay helps to build

a flexible power sequencing design on a PCB.

The Reg08[7:6] bits controls this delay time and see Table 16 for available options.

On-the-fly Reference Programming

By using the Servo Reference Control block, the main-buck supports on-the-fly programming of the Output Voltage

Reference and Output Current Reference. That means, through the I

2C, the main-buck can accept a target value change of

these two reference sources while the iEN is logic=H.

See Main-buck Power-Good.

Negative Transition with RDIS

In the Output Voltage Reference is programmed for a lower target voltage from the current output, it may take long time

period to reach to the new target value when very little load current / activities there. To accelerate such light-load negative

transition, the device utilizes the Output Discharge Resistor block when the Reg09[5] bit is logic-H.

Main-buck EMI Tune-up

For the purpose of improving its EMI performance, this main-buck provides programmable switching node slew rate. By

changing the Reg0E[3:2] bits, an application system designer can balance the tradeoff between its power conversion

efficiency and its EMI noise level. By selecting slower transient rate, the noise performance improves; faster transient rate

improves the efficiency. See Table 28 for the available options.

Output Current Protections

In this datasheet, following three function names refer to clearly different meanings and behaviors of the

device.

Programmable Current Limit

The Programmable Current Limit function is a regulation control of the main-buck output current at a

programming target value (CC: constant-current operation), within a safe operation area (SOA) of the

device. This means a continuous operation at this programmable current limit is safe and supported.

Cycle-by-cycle Current Limit

The Cycle-by-cycle Current Limit protection is a hard limit of the main-buck output current. The

threshold of this protection is beyond the design and safe operation area of the device. Repeated events

of this protection will degrade or damage the device permanently.

Over-Current Protection

The Over-Current Protection (OCP) is a superset of the cycle-by-cycle current limit protection. The OCP

is also beyond the design and safe operation area of the device and repeated OCP events will degrade

or damage the device permanently.

Cycle-by-cycle Current Limit

The cycle-by-cycle current limit protection monitors current flow on the integrated high-side and low-side FET devices

at every PWM cycle. When the high-side FET current flow exceeds the IOCP(CBC,high) threshold, the protection forces the

ACT41000 Data Sheet, Rev. B, 01-Apr-2022

Subject to change without notice

ACT41000-103 Datasheet(PDF) 45 Page - Qorvo, Inc

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